DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/20/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-10 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek (US 2022/0208787).
Regarding claim 1, Baek discloses, in at least figures 4, 7, 12-13 and related text, a NAND flash device ([54]) comprising:
a peripheral circuit (PCS, [47]) including a transistor (TR, [106]), a substrate (52, [104]), and a device isolation region (54, [105]) on the substrate (52, [104]), wherein
the device isolation region (54, [105]) defines an active region (AC, [105]) of the substrate (52, [104]),
the transistor (TR, [106]) includes a first gate structure (PG, 106]) on the active region (AC, [105]),
the transistor (TR, [106]) includes a plurality of source and drain regions (PSD, [106]) extending in a first direction (x direction, figures) in the active region (AC, [105]) on both sides of the first gate structure (PG, [106]),
the plurality of source and drain regions (PSD of TR1, [106], [127]) include a first lightly-doped source and drain region (306a, [133]) and a second lightly-doped source and drain region (306b, [133]),
the first lightly-doped source and drain region (306a, [133]) is adjacent to the first gate structure (314, [128]) and has a first width (IL3, [134]) in a second direction (y direction, figures),
the second direction (y direction, figures) is perpendicular to the first direction (x direction, figures),
the second lightly-doped source and drain region (306b, [133]) is integrally connected to the first lightly-doped source and drain region (306a, [133]),
the second lightly-doped source and drain region (306b, [133]) is arranged farther from the first gate structure (314, [128]) than the first lightly-doped source and drain region (306a, [133]),
the second lightly-doped source and drain region (306b, [133]) has a second width (IL4, [134]) in the second direction (y direction, figures), and
the second width (IL4, [134]) is less than the first width (IL3, [134]).
Regarding claim 2, Baek discloses the NAND flash device of claim 1 as described above.
Baek further discloses, in at least figures 4, 7, 12-13 and related text, the first lightly-doped source and drain region (306a, [133]) has a third width (width of 306a in x direction, figures) in the first direction (x direction, figures),
the second lightly-doped source and drain region (306b, [133]) has a fourth width (width of 306b in x direction, figures) in the first direction (x direction, figures), and
the fourth width (width of 306b in x direction, figures) is greater than or equal to the third width (width of 306a in x direction, figures) (figures).
Regarding claim 3, Baek discloses the NAND flash device of claim 1 as described above.
Baek further discloses, in at least figures 4, 7, 12-13 and related text, a part of the first lightly-doped source and drain region (306a, [133]) overlaps the first gate structure (314, [128]).
Regarding claim 4, Baek discloses the NAND flash device of claim 1 as described above.
Baek further discloses, in at least figures 4, 11-13 and related text, the plurality of source and drain regions (PSD of TR1, [106], [127]) include a first heavily-doped source and drain region (310, [130]) buried in the second lightly-doped source and drain region (306b, [133]),
the peripheral circuit (PCS, [47]) includes a first source and drain contact on the first heavily-doped source and drain region (310, [130]), and
the first source and drain contact (136, [138]) is configured to apply a voltage to the first heavily- doped source and drain region (310, [130]).
Regarding claim 7, Baek discloses the NAND flash device of claim 1 as described above.
Baek further discloses, in at least figures 4, 7, 12-13 and related text, the first gate structure (314, [128]) has a fifth width (width of 314 in y direction, figures) in the second direction (y direction, figures), and
the fifth width (width of 314 in y direction, figures) is greater than the second width (IL4, [134]) of the second lightly-doped source and drain region (306b, [133]) in the second direction (y direction, figures).
Regarding claim 8, Baek discloses the NAND flash device of claim 1 as described above.
Baek further discloses, in at least figures 4, 7, 12-13 and related text, the active region (AC/304, [105], [128]) includes a tapered trench,
the device isolation region (54/302, [105], [128]) is in the tapered trench, and
the plurality of source and drain regions (PSD of TR/TR1, [106], [127]) are surrounded by the isolation region (54/302, [105], [128]).
Regarding claim 9, Baek discloses the NAND flash device of claim 1 as described above.
Baek further discloses, in at least figures 4, 7, 12-13 and related text, the peripheral circuit (PCS, [47]) includes a second gate structure (PG/314 of TR (TR1) adjacent to leftmost TR (TR1), [106], [127], [128], figures) separated from the first gate structure (PG/314 of leftmost TR (TR1), [106], [127], [128], figures) in the first direction (x direction, figures),
the active region (AC/304, [105], [128]) includes a third lightly-doped source and drain region (308, [130]) in a portion of the substrate (52, [104]), and
when viewed from a third direction (z direction, figures) perpendicular to an upper surface of the active region (AC/304, [105], [128]), the third lightly-doped source and drain region (308, [130]) is between the first gate structure (PG/314 of leftmost TR (TR1), [106], [127], [128], figures) and the second gate structure (PG/314 of TR (TR1) adjacent to leftmost TR (TR1), [106], [127], [128], figures) and a width of the third lightly-doped source and drain region (308, [130]) in the second direction (y direction, figures) is equal to the first width (IL3, [134]) in the second direction (y direction, figures).
Regarding claim 10, Baek discloses the NAND flash device of claim 9 as described above.
Baek further discloses, in at least figures 4, 7, 12-13 and related text, the active region (AC/304, [105], [128]) includes a second heavily-doped source and drain region (312, [130]) buried in the third lightly-doped source and drain region (308, [130]), and
the peripheral circuit (PCS, [47]) includes a second source and drain contact (320, [138]) on the second heavily- doped source and drain region (312, [130]) and configured to apply a voltage to the second heavily-doped source and drain region (312, [130]).
Regarding claim 19, Baek discloses, in at least figures 4, 7, 12-13 and related text, a NAND flash device ([54]) comprising:
a peripheral circuit (PCS, [47]) including a plurality of transistors (TR, [106]) on a substrate (52, [104]); and
a memory cell array (CAS, [46]) configured to controlled by the peripheral circuit (PCS, [47]), wherein
the peripheral circuit (PCS, [47]) includes a tapered trench (trench for 54, figures) in the substrate (52, [104]), a device isolation region (54, [105]) in the tapered trench (trench for 54, figures) and defining an active region (AC, [105]) of the substrate (52, [104]), a pair of gate structures (PG/314 of two adjacent TR (TR1), [106], [127], [128], figures) arranged side by side in a first direction (x direction, figures) on the active region (AC, [105]), and a source and drain region (PSD, [106]) in the active region (AC, [105]),
the pair of gate structures (PG/314 of two adjacent TR (TR1), [106], [127], [128], figures) are separated from each other and extend in a second direction (y direction, figures),
the second direction (y direction, figures) is perpendicular to the first direction (x direction, figures),
the source and drain region (PSD, [106]) extends in the first direction (x direction, figures) in the active region (AC, [105]) on both sides of each of the pair of gate structures (PG/314 of two adjacent TR (TR1), [106], [127], [128], figures),
the source and drain region (PSD, [106], [127]) includes a lightly-doped source and drain region (306, [133]) and a first heavily-doped source and drain region (310, [130]),
the lightly-doped source and drain region (306, [133]) includes a first lightly-doped source and drain region (306a, [133]) in the substrate (52, [104]) in a region adjacent to each of the pair of gate structures (PG/314 of two adjacent TR (TR1), [106], [127], [128], figures) and a second lightly-doped source and drain region (306b, [133]) farther from each of the pair of gate structures (PG/314 of two adjacent TR (TR1), [106], [127], [128], figures) than the first lightly-doped source and drain region (306a, [133]),
the first heavily-doped source and drain region (310, [130]) is in the second lightly-doped source and drain region (306b, [133]),
the first heavily-doped source and drain region (310, [130]) is more heavily doped than the lightly- doped source and drain region (306, [130]),
the first lightly-doped source and drain region (306a, [133]) has a first width in the first direction (x direction, figures) and a second width in the second direction (y direction, figures),
the second lightly-doped source and drain region (306b, [133]) has a third width in the first direction (x direction, figures) and a fourth width in the second direction (y direction, figures),
the first width is less than the third width (figures 12-13), and
the second width is greater than the fourth width (figures 12-13).
Allowable Subject Matter
Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 5 that recite "the peripheral circuit includes an isolation impurity region in the substrate, the isolation impurity region surrounds the plurality of source and drain regions when viewed from a third direction perpendicular to an upper surface of the active region, and a first separation distance in the second direction between the first lightly-doped source and drain region and the isolation impurity region is less than a second separation distance in the second direction between the second lightly-doped source and drain region and the isolation impurity region" in combination with other elements of the base claims 1 and 5.
Claims 11-18 are allowed because the prior art of record neither anticipates nor render obvious the limitations of the base claims 11 that recite "the second width is reduced as a distance increases from the pair of gate structures" in combination with other elements of the base claims 11.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 19 and 20 that recite "the peripheral circuit includes an isolation impurity region in the substrate, the isolation impurity region surrounds the source and drain region when viewed from a third direction perpendicular to an upper surface of the source and drain region, a first separation distance in the second direction between the first lightly-doped source and drain region and the isolation impurity region is less than a second separation distance in the second direction between the second lightly-doped source and drain region and the isolation impurity region, the first lightly-doped source and drain region and the second lightly-doped source and drain region include an impurity of a first conductivity type, the isolation impurity region includes an impurity of a second conductivity type, and the second conductivity type is different from the first conductivity type" in combination with other elements of the base claims 19 and 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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