DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Applicant's election without traverse of claims 1-4, 6, 7, 11-15, and 17-19 in the reply filed on 9/2/2026 is acknowledged.
3. Claims 5, 8-10, 16, and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 2020/0258891) (hereafter Huang).
Regarding claim 1, Huang discloses a semiconductor device, comprising:
a substrate 50 (Fig. 6, paragraph 0025) including:
an active region (56, 60, and 64 in Fig. 6, paragraph 0025) including a central active region 64 (Fig. 6, paragraph 0025) extending in a first direction (horizontal direction in Fig. 6), a first extended active region (top portion of 60 in Fig. 6, paragraph 0025) extending from a first edge of the central active region 64 (Fig. 6) in a second direction (vertical direction in Fig. 6) perpendicular to the first direction (horizontal direction in Fig. 6), a second extended active region (top portion of 56 in Fig. 6, paragraph 0025) extending from a second edge of the central active region 64 (Fig. 6) in the second direction (vertical direction in Fig. 6), a third extended active region (bottom portion of 60 in Fig. 6) extending from a third edge of the central active region 64 (Fig. 6) in the second direction (vertical direction in Fig. 6), and a fourth extended active region (bottom portion of 56 in Fig. 6) extending from a fourth edge of the central active region 64 (Fig. 6) in the second direction (vertical direction in Fig. 6), and
a device isolation layer 68 (Fig. 6, paragraph 0026) defining the active region (56, 60, and 64 in Fig. 6); and
a first gate structure 78 (Fig. 6, paragraph 0027), a second gate structure 76 (Fig. 6, paragraph 0027), a third gate structure 80 (Fig. 6, paragraph 0027), and a fourth gate structure 74 (Fig. 6, paragraph 0027) on the active region (56, 60, and 64 in Fig. 6) and spaced apart from one another, wherein:
the central active region 64 (Fig. 6), the first extended active region (top portion of 60 in Fig. 6), and the first gate structure 78 (Fig. 6) constitute a first pass transistor (PG3 in Fig. 6, paragraph 0027), the central active region 64 (Fig. 6), the second extended active region (top portion of 56 in Fig. 6), and the second gate structure 76 (Fig. 6) constitute a second pass transistor (PD21 in Fig. 6, paragraph 0021), the central active region 64 (Fig. 6), the third extended active region (bottom portion of 60 in Fig. 6), and the third gate structure 80 (Fig. 6) constitute a third pass transistor (PG4 in Fig. 6, paragraph 0027), and the central active region 64 (Fig. 6), the fourth extended active region (bottom portion of 56 in Fig. 6), and the fourth gate structure 74 (Fig. 6) constitute a fourth pass transistor (PD22 in Fig. 6, paragraph 0021),
the first to fourth pass transistors (PG3, PD21, PG4, and PD22 in Fig. 6) share one drain region (see box with X of 64 in Fig. 6) on the central active region 64 (Fig. 6), and
the active region (56, 60, and 64 in Fig. 6) has an H shape in a plan view.
Regarding claim 2, Huang further discloses the semiconductor device as claimed in claim 1, wherein each of the first to fourth gate structures (78, 76, 80, and 74 in Fig. 6) independently has a rectangular shape (see Fig. 6) or an L shape in a plan view.
Regarding claim 3, Huang further discloses the semiconductor device as claimed in claim 1, further comprising a drain contact on the drain region (see box with X of 64 in Fig. 6), wherein the drain contact is on a plane parallel to the first direction (horizontal direction in Fig. 6) and the second direction (vertical direction in Fig. 6) and in an oblique direction with respect to the first to fourth gate structures (78, 76, 80, and 74 in Fig. 6).
Regarding claim 4, Huang further discloses the semiconductor device as claimed in claim 1, wherein the first to fourth pass transistors (PG3, PD21, PG4, and PD22 in Fig. 6) each include high voltage pass transistors.
Regarding claim 6, Huang further discloses the semiconductor device as claimed in claim 1, wherein an isolation region (lower portion of 68 in Fig. 6) in the substrate 50 (Fig. 6) under the device isolation layer 68 (Fig. 6), wherein the isolation region (lower portion of 68 in Fig. 6) includes: a first isolation region (lower portion of 68 in Fig. 6) surrounding the active region (56, 60, and 64 in Fig. 6), and a first extended isolation region (portion of 68 between top 60 and top 56 in Fig. 6) and a second extended isolation region (portion of 68 between bottom 60 and bottom 56 in Fig. 6) extending from the first isolation region toward the central active region 64 (Fig. 6) in the second direction (vertical direction in Fig. 6) and spaced apart from each other in the second direction.
Regarding claim 7, Huang further discloses the semiconductor device as claimed in claim 6, further comprising a first contact (box with X of top portion of 60 in Fig. 6) on the first extended active region (top portion of 60 in Fig. 6), a second contact (box with X of top portion of 56 in Fig. 6) on the second extended active region (top portion of 56 in Fig. 6), a third contact (box with X of bottom portion of 60 in Fig. 6) on the third extended active region (bottom portion of 60 in Fig. 6), and a fourth contact (box with X of bottom portion of 56 in Fig. 6) on the fourth extended active region (bottom portion of 56 in Fig. 6), wherein: the first extended isolation region (portion of 68 between top 60 and top 56 in Fig. 6) is between the first contact and the second contact, and the second extended isolation region (portion of 68 between bottom 60 and bottom 56 in Fig. 6) is between the third contact and the fourth contact.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2020/0258891) (hereafter Huang), in view of Kim et al. (US 2021/0202456) (hereafter Kim).
Regarding claim 11, Huang discloses a semiconductor device, comprising:
a peripheral circuit structure 300 (Fig. 6); and
wherein:
the peripheral circuit structure 300 (Fig. 6) includes:
a substrate 50 (Fig. 6, paragraph 0025) including:
an active region (56, 60, and 64 in Fig. 6, paragraph 0025) including a central active region 64 (Fig. 6, paragraph 0025) extending in a first direction (horizontal direction in Fig. 6), a first extended active region (top portion of 60 in Fig. 6, paragraph 0025) extending from a first edge of the central active region 64 (Fig. 6) in a second direction (vertical direction in Fig. 6) perpendicular to the first direction (horizontal direction in Fig. 6), a second extended active region (top portion of 56 in Fig. 6, paragraph 0025) extending from a second edge of the central active region 64 (Fig. 6) in the second direction (vertical direction in Fig. 6), a third extended active region (bottom portion of 60 in Fig. 6) extending from a third edge of the central active region 64 (Fig. 6) in the second direction (vertical direction in Fig. 6), and a fourth extended active region (bottom portion of 56 in Fig. 6) extending from a fourth edge of the central active region 64 (Fig. 6) in the second direction (vertical direction in Fig. 6), and
a device isolation layer 68 (Fig. 6, paragraph 0026) defining the active region (56, 60, and 64 in Fig. 6); and
a first gate structure 78 (Fig. 6, paragraph 0027), a second gate structure 76 (Fig. 6, paragraph 0027), a third gate structure 80 (Fig. 6, paragraph 0027), and a fourth gate structure 74 (Fig. 6, paragraph 0027) on the active region (56, 60, and 64 in Fig. 6) and spaced apart from one another, wherein:
the central active region 64 (Fig. 6), the first extended active region (top portion of 60 in Fig. 6), and the first gate structure 78 (Fig. 6) constitute a first pass transistor (PG3 in Fig. 6, paragraph 0027), the central active region 64 (Fig. 6), the second extended active region (top portion of 56 in Fig. 6), and the second gate structure 76 (Fig. 6) constitute a second pass transistor (PD21 in Fig. 6, paragraph 0021), the central active region 64 (Fig. 6), the third extended active region (bottom portion of 60 in Fig. 6), and the third gate structure 80 (Fig. 6) constitute a third pass transistor (PG4 in Fig. 6, paragraph 0027), and the central active region 64 (Fig. 6), the fourth extended active region (bottom portion of 56 in Fig. 6), and the fourth gate structure 74 (Fig. 6) constitute a fourth pass transistor (PD22 in Fig. 6, paragraph 0021),
the first to fourth pass transistors (PG3, PD21, PG4, and PD22 in Fig. 6) share one drain region (see box with X of 64 in Fig. 6) on the central active region 64 (Fig. 6), and
the active region (56, 60, and 64 in Fig. 6) has an H shape in a plan view.
Huang does not disclose a cell array structure overlapping the peripheral circuit structure in a vertical direction and including a first memory cell block, a second memory cell block, a third memory cell block, and a fourth memory cell block.
Kim disclose a cell array structure (CELL in Fig. 22) overlapping the peripheral circuit structure (PERI in Fig. 22) in a vertical direction and including (see 1 in Fig. 3B, paragraph 0063, wherein “memory cell array”) a first memory cell block, a second memory cell block, a third memory cell block, and a fourth memory cell block (BLK0-BLKn in Fig. 3B, paragraph 0065).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang to form a cell array structure overlapping the peripheral circuit structure in a vertical direction and including a first memory cell block, a second memory cell block, a third memory cell block, and a fourth memory cell block, as taught by Kim, since the memory cell array 1 (Kim, Fig. 3B, paragraph 0063) may include a plurality of memory blocks BLK0 to BLKn (Kim, Fig. 3B, paragraph 0063) that is a unit of data erase.
Regarding claim 12, Huang in view of Kim discloses the semiconductor device as claimed in claim 11, however Huang does not disclose the cell array structure further includes a plurality of first bonding pads, the peripheral circuit structure further includes a plurality of second bonding pads, and the plurality of first bonding pads are bonded to the plurality of second bonding pads.
Kim discloses the cell array structure (CELL in Fig. 22) further includes a plurality of first bonding pads 372b (Fig. 22, paragraph 0161), the peripheral circuit structure (PERI in Fig. 22) further includes a plurality of second bonding pads 272b (Fig. 22, paragraph 0161), and the plurality of first bonding pads 372b (Fig. 22) are bonded to the plurality of second bonding pads 272b (Fig. 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang to form the cell array structure further includes a plurality of first bonding pads, the peripheral circuit structure further includes a plurality of second bonding pads, and the plurality of first bonding pads are bonded to the plurality of second bonding pads, as taught by Kim, since, in the word line bonding area WLBA (Kim, Fig. 22, paragraph 0161), the lower bonding metals 271b and 272b (Kim, Fig. 22, paragraph 0161) in the peripheral circuit region PERI (Kim, Fig. 22, paragraph 0161) may be electrically bonded to upper bonding metals 371b and 372b (Kim, Fig. 22, paragraph 0161) of the cell region CELL (Kim, Fig. 22, paragraph 0161).
Regarding claim 13, Huang in view of Kim discloses the semiconductor device as claimed in claim 11, however Huang does not disclose the cell array structure includes a cell stack structure and a cell substrate, and the cell substrate is between the cell stack structure and the peripheral circuit structure.
Kim discloses the cell array structure (CELL in Fig. 22) includes a cell stack structure 330 (Fig. 22) and a cell substrate 315 (Fig. 22), and the cell substrate is between the cell stack structure 330 (Fig. 22) and the peripheral circuit structure (PERI in Fig. 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang to form the cell array structure includes a cell stack structure and a cell substrate, and the cell substrate is between the cell stack structure and the peripheral circuit structure, as taught by Kim, since, in the word line bonding area WLBA (Kim, Fig. 22, paragraph 0161), the lower bonding metals 271b and 272b (Kim, Fig. 22, paragraph 0161) in the peripheral circuit region PERI (Kim, Fig. 22, paragraph 0161) may be electrically bonded to upper bonding metals 371b and 372b (Kim, Fig. 22, paragraph 0161) of the cell region CELL (Kim, Fig. 22, paragraph 0161).
Regarding claim 14, Huang in view of Kim discloses the semiconductor device as claimed in claim 11, however Huang does not disclose one of the first to fourth pass transistors is configured to transmit an operating voltage to one of the first to fourth memory cell blocks corresponding to the one of the first to fourth pass transistors based on a block selection signal.
Kim discloses one of the first to fourth pass transistors 394 (Fig. 22, paragraph 0166, wherein “row decoder”) is configured to transmit (see paragraph 0065, wherein “The row decoder 2 may select one of the memory blocks BLK0 to BLKn of the memory cell array 1 in accordance with the address information, and may select one of the word lines of the selected memory block“) an operating voltage to one of the first to fourth memory cell blocks (BLK0-BLKn in Fig. 3B, paragraph 0065) corresponding to the one of the first to fourth pass transistors based on a block selection signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang to form one of the first to fourth pass transistors is configured to transmit an operating voltage to one of the first to fourth memory cell blocks corresponding to the one of the first to fourth pass transistors based on a block selection signal, as taught by Kim, since the row decoder 2 (Kim, Fig. 3B, paragraph 0065) may provide a word line voltage generated from a voltage generation circuit to each of the selected word lines and the non-selected word lines in response to the control of a control circuit.
Regarding claim 15, Huang further discloses the semiconductor device as claimed in claim 11, wherein each of the first to fourth gate structures (78, 76, 80, and 74 in Fig. 6) independently has a rectangular shape (see Fig. 6) or an L shape in a plan view.
Regarding claim 17, Huang further discloses the semiconductor device as claimed in claim 11, further comprising a drain contact (dash lines in box with X of 64 in Fig. 6, paragraph 0027, wherein “the metal lines are marked by dashed lines in FIG. 6”) on the drain region (see box with X of 64 in Fig. 6), wherein the drain contact (dash lines in box with X of 64 in Fig. 6) is on a plane parallel to the first direction (horizontal direction in Fig. 6) and the second direction (vertical direction in Fig. 6) and in an oblique direction with respect to the first to fourth gate structures (78, 76, 80, and 74 in Fig. 6).
Regarding claim 18, Huang further discloses the semiconductor device as claimed in claim 11, wherein an isolation region (lower portion of 68 in Fig. 6) in the substrate 50 (Fig. 6) under the device isolation layer 68 (Fig. 6), wherein the isolation region (lower portion of 68 in Fig. 6) includes: a first isolation region (lower portion of 68 in Fig. 6) surrounding the active region (56, 60, and 64 in Fig. 6), and a first extended isolation region (portion of 68 between top 60 and top 56 in Fig. 6) and a second extended isolation region (portion of 68 between bottom 60 and bottom 56 in Fig. 6) extending from the first isolation region toward the central active region 64 (Fig. 6) in the second direction (vertical direction in Fig. 6) and spaced apart from each other in the second direction.
Regarding claim 19, Huang discloses an electronic system, comprising:
the semiconductor device 300 (Fig. 6) includes:
a substrate 50 (Fig. 6, paragraph 0025) including:
an active region (56, 60, and 64 in Fig. 6, paragraph 0025) including a central active region 64 (Fig. 6, paragraph 0025) extending in a first direction (horizontal direction in Fig. 6), a first extended active region (top portion of 60 in Fig. 6, paragraph 0025) extending from a first edge of the central active region 64 (Fig. 6) in a second direction (vertical direction in Fig. 6) perpendicular to the first direction (horizontal direction in Fig. 6), a second extended active region (top portion of 56 in Fig. 6, paragraph 0025) extending from a second edge of the central active region 64 (Fig. 6) in the second direction (vertical direction in Fig. 6), a third extended active region (bottom portion of 60 in Fig. 6) extending from a third edge of the central active region 64 (Fig. 6) in the second direction (vertical direction in Fig. 6), and a fourth extended active region (bottom portion of 56 in Fig. 6) extending from a fourth edge of the central active region 64 (Fig. 6) in the second direction (vertical direction in Fig. 6), and
a device isolation layer 68 (Fig. 6, paragraph 0026) defining the active region (56, 60, and 64 in Fig. 6); and
a first gate structure 78 (Fig. 6, paragraph 0027), a second gate structure 76 (Fig. 6, paragraph 0027), a third gate structure 80 (Fig. 6, paragraph 0027), and a fourth gate structure 74 (Fig. 6, paragraph 0027) on the active region (56, 60, and 64 in Fig. 6) and spaced apart from one another, wherein:
the central active region 64 (Fig. 6), the first extended active region (top portion of 60 in Fig. 6), and the first gate structure 78 (Fig. 6) constitute a first pass transistor (PG3 in Fig. 6, paragraph 0027), the central active region 64 (Fig. 6), the second extended active region (top portion of 56 in Fig. 6), and the second gate structure 76 (Fig. 6) constitute a second pass transistor (PD21 in Fig. 6, paragraph 0021), the central active region 64 (Fig. 6), the third extended active region (bottom portion of 60 in Fig. 6), and the third gate structure 80 (Fig. 6) constitute a third pass transistor (PG4 in Fig. 6, paragraph 0027), and the central active region 64 (Fig. 6), the fourth extended active region (bottom portion of 56 in Fig. 6), and the fourth gate structure 74 (Fig. 6) constitute a fourth pass transistor (PD22 in Fig. 6, paragraph 0021),
the first to fourth pass transistors (PG3, PD21, PG4, and PD22 in Fig. 6) share one drain region (see box with X of 64 in Fig. 6) on the central active region 64 (Fig. 6), and
the active region (56, 60, and 64 in Fig. 6) has an H shape in a plan view.
Huang does not disclose a main substrate;
a semiconductor device on the main substrate; and
a controller electrically connected to the semiconductor device on the main substrate.
Kim discloses a main substrate 210 (Fig. 22, paragraph 0168);
a semiconductor device 394 (Fig. 22, paragraph 0166) on the main substrate 210 (Fig. 22; and
a controller (see paragraph 0064, wherein “A peripheral circuit (not shown) which controls the memory cell array of the cell region CELL may be formed in the peripheral circuit region PERI”) electrically connected (see paragraph 0065, wherein “the row decoder 2 may provide a word line voltage generated from a voltage generation circuit (not shown) to each of the selected word lines and the non-selected word lines in response to the control of a control circuit (not shown)”) to the semiconductor device 394 (Fig. 22) on the main substrate 210 (Fig. 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Huang to form a main substrate; a semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate, as taught by Kim, since a peripheral circuit (Kim, paragraph 0064) which controls the memory cell array of the cell region CELL (Kim, Fig. 22, paragraph 0064) may be formed in the peripheral circuit region PERI (Kim, Fig. 22, paragraph 0064).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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