DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The applicant’s amended claims overcome the previous objection to the figures.
The applicant argues on page 10 that “[t]he claim affirmatively requires that the electronic components and vias together define a conductive path forming a loop area, and further requires that the loop area be oriented entirely orthogonal to the die. This is a specific geometric and electrical relationship that constrains how current flows through the structure, not merely the presence of vias or vertical interconnects. …. Moreover, the claim requires that the loop area be ‘entirely orthogonal to the die.’ The cited references do not disclose any conductive loop having a plane oriented orthogonal to the die. To the contrary, the references primarily describe lateral routing structures (e.g., redistribution layers or substrate traces) that inherently define current paths extending parallel to the die surface, or combinations of vertical and lateral paths that do not form a loop having the claimed orientation.”
As a first matter, claim 1 recites “the conductive path forming a loop area oriented entirely orthogonal to the die”. This would seem to be different to what the applicant argues, that “to the contrary [of the claimed arrangement], the references primarily describe lateral routing structures (e.g., redistribution layers or substrate traces) that inherently define current paths extending parallel to the die surface”. It is not clear how there could be a current loop without a horizontal component; as the current has to go all the way around the loop, the only way it would not have a horizontal component would be if the current travelled vertically down and then up in exactly the same vertical location, which is not usually called a “loop”. Is the applicant here arguing that no horizontal portion of the current path is permitted? As it is not clear what exactly is required for the claimed conductive path forming a loop area oriented entirely orthogonal to the die, based on the applicant’s arguments, the examiner has objected to the drawings and included an enablement rejection.
The specification refers to this feature at [0025]: “Embodiments of the present disclosure include electronic components 108 disposed on a top surface of the die 100/over mold 102 with direct vias 114 to the die 100. Such architecture produces smaller loop area with low inductance and smaller EMI coupling or emission regions. In one aspect, the shorter length of the loop area is advantageous to reduce inductance and EMI coupling; furthermore, the orientation of the loop area (entirely orthogonal to the die 100 as compared to partially parallel to the die 100) may also reduce inductance and EMI coupling, especially in high frequency applications (e.g., K band or higher).” This is (apparently) shown in FIG. 2, with currently travelling vertically through the vias that connect the electronic component to the die:
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The loop is apparently composed of these currents, together with (unillustrated) horizontal currents that complete the loop:
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The only thing that determines that the current loop is orthogonal to the die is that current is carried through the vertical vias connecting the electronic components to the die. This is disclosed by, e.g., DeLaCruz. The area connected by the vias will be a vertical plane, which will define the current loop. All of these devices will necessarily have currents going up and currents going down, as otherwise there would rapidly be large charge accumulations on the electronic device. Probably any device, passive or active, will have input and output vias which will form a current loop. Thus it appears to the examiner that all of the prior art references will read on this claim feature.
If the applicant is invited to contact the examiner if the applicant believes that any rejections are not warranted.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the conductive path forming a loop area oriented entirely orthogonal to the die must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 6-11, 13-18, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 recites “a plurality of electronic components disposed on the top surface and electrically coupled to the die through the plurality of vias; wherein: the plurality of electronic components and the plurality of vias define a conductive path between the plurality of electronic components and the die, the conductive path forming a loop area oriented entirely orthogonal to the die”. The disclosure related to this in the specification is at [0025] and FIG. 2. The applicant argues on page 10 of the response that “to the contrary [of the claimed subject matter], the references primarily describe lateral routing structures (e.g., redistribution layers or substrate traces) that inherently define current paths extending parallel to the die surface”. The applicant has not taught how to form a current loop that does not have a current path parallel to the die surface. In fact, the applicant has not explicitly shown or taught what the current loop is, or how it has a loop area entirely orthogonal to the die. Thus those in the art would not be enabled to practice the invention including this feature.
The remaining independent claims have this feature and are rejected for the same reason. The other claims are rejected based on their dependencies.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-11, 13-18, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a plurality of electronic components disposed on the top surface and electrically coupled to the die through the plurality of vias; wherein: the plurality of electronic components and the plurality of vias define a conductive path between the plurality of electronic components and the die, the conductive path forming a loop area oriented entirely orthogonal to the die”. The applicant argues on page 10 of the response that “to the contrary [of the claimed subject matter], the references primarily describe lateral routing structures (e.g., redistribution layers or substrate traces) that inherently define current paths extending parallel to the die surface”. As this is not disclosed or enabled, it would not be clear to those in the art what the scope of claim 1 requires.
Claim 1 recites “a plurality of vias transiting a top surface of the over mold, disposed to engage electronic components on the top surface and produce direct electronic connectivity to a top surface of the die; and a plurality of electronic components disposed on the top surface and electrically coupled to the die through the plurality of vias”. The “plurality of electronic components” does not refer back to the previously recited “electronic components”, and thus it is not clear whether these are the same components or different components. For present purposes, the examiner will assume that they are the same components.
Claims 7 and 14 have analogous recitations are rejected for the same reason.
The remaining claims are rejected based on their dependencies.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over DeLaCruz in evidence of or in view of Cornelius.
Claim 1: DeLaCruz discloses
a die (145);
an over mold (143) surrounding the die;
and a plurality of vias (231) transiting a top surface of the over mold, disposed to engage electronic components (165) on the top surface and produce electronic connectivity to a top surface of the die;
a plurality of electronic components (165) disposed on the top surface and electrically coupled to the die through the plurality of vias;
wherein a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board (through interconnects 17).
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Claim 1 recites “a plurality of electronic components disposed on the top surface and electrically coupled to the die through the plurality of vias”. DeLaCruz does not explicitly show a plurality of electronic components 165; however, this is mere multiplication of parts, and would not be a source of patentable distinction over DeLaCruz.
Claim 1 also recites that the plurality of electronic components and the plurality of vias define a conductive path between the plurality of electronic components and the die, the conductive path forming a loop area oriented entirely orthogonal to the die. DeLaCruz discloses multiple vertical vias 231 connected to the die 145. The examiner takes official notice that there will of necessity be input and output signals, and thus it there will be a current loop. All of these devices will necessarily have currents going up and currents going down, as otherwise there would rapidly be large charge accumulations on the electronic device. Any device, passive or active, will have input and output vias which will form a current loop.
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Alternatively, see Cornelius, FIG. 3, which shows a current loop 302 formed by two vias and an electronic component (capacitor 108; note that 165 of DeLaCruz can be a passive element ([0062]), of which capacitors are a very common type ([0003])). It would have been inherent or very obvious for a current loop to be formed. The area of the current loop would be determined by an input via and an output via, which are vertical, and the area defined by those vertical vias would be an area that is entirely orthogonal to the die (having a horizontal main surface).
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Furthermore, DeLaCruz discloses a structure which is essentially identical to the applicant’s disclosure (FIG. 2). “Where, as here, the claimed and prior art products are identical or substantially identical, or are produced by identical or substantially identical processes, the PTO can require an applicant to prove that the prior art products do not necessarily or inherently possess the characteristics of his claimed product. See In re Ludtke, supra. Whether the rejection is based on ‘inherency’ under 35 USC 102, on ‘prima facie obviousness’ under 35 USC 103, jointly or alternatively, the burden of proof is the same, and its fairness is evidenced by the PTO's inability to manufacture products or to obtain and compare prior art products.” In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433-434 (CCPA 1977).
Claim 2: a wafer level chip scale package (WLCSP) and a wafer level fanout package (WLFO) are product-by-process terms; that is, they are limiting on the resulting device only as to the resulting structure. Those in the art would recognize that the structure of DeLaCruz could be formed by a WLCSP process; that is, the fan out substrate 19 could be attached to the chip while on the wafer.
Claim 3: DeLaCruz discloses an interposer (19), wherein the die and over mold are disposed on a top surface of the interposer and the over mold at least partially encloses the interposer. The substrate 19 has bonding pads on the bottom, and thus can be attached to another substrate or circuit board; thus the substrate 19 can be considered an interposer, that is, a substrate that interposes between the chip and another substrate.
Claim 4: DeLaCruz discloses one or more vias (131) disposed to provide electronic connectivity between the top surface of the over mold and the top surface of the interposer without engaging the die.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 8, 10, 11, 14, 15, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over DeLaCruz in view of Kim, US 2022/0157676 A1, and in evidence or in view of Cornelius.
Claim 7: DeLaCruz discloses
a die (145);
an over mold (143) surrounding the die;
and a plurality of vias (231) transiting a top surface of the over mold, disposed to engage electronic components (165) on the top surface and produce direct electronic connectivity to a top surface of the die;
and a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board (through interconnects 17).
Claim 7 recites a plurality of electronic components disposed on the top surface and electrically coupled to the die through the plurality of vias, while DeLaCruz only illustrates a single device 165. However, having multiple elements would have been merely multiplication of parts. See also Kim, which shows that it was known to have multiple devices connected over the die:
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Claim 7 also recites that the plurality of electronic components and the plurality of vias define a conductive path between the plurality of electronic components and the die, the conductive path forming a loop area oriented entirely orthogonal to the die. DeLaCruz discloses multiple vertical vias 231 connected to the die 145. . DeLaCruz discloses multiple vertical vias 231 connected to the die 145. The examiner takes official notice that there will of necessity be input and output signals, and thus it there will a current loop. All of these devices will necessarily have currents going up and currents going down, as otherwise there would rapidly be large charge accumulations on the electronic device. Any device, passive or active, will have input and output vias which will form a current loop. Alternatively, see Cornelius, FIG. 3, which shows a current loop formed by two vias and an electronic component (capacitor 108; note that 165 of DeLaCruz can be a passive element ([0062]), of which capacitors are a very common type ([0003])). It would have been inherent or very obvious for a current loop to be formed. The area of the current loop would be determined by an input via and an output via, which are vertical, and the area defined by those vertical vias would be an area that is entirely orthogonal to the die (having a horizontal main surface).
Furthermore, DeLaCruz discloses a structure which is essentially identical to the applicant’s disclosure (FIG. 2). “Where, as here, the claimed and prior art products are identical or substantially identical, or are produced by identical or substantially identical processes, the PTO can require an applicant to prove that the prior art products do not necessarily or inherently possess the characteristics of his claimed product. See In re Ludtke, supra. Whether the rejection is based on ‘inherency’ under 35 USC 102, on ‘prima facie obviousness’ under 35 USC 103, jointly or alternatively, the burden of proof is the same, and its fairness is evidenced by the PTO's inability to manufacture products or to obtain and compare prior art products.” In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433-434 (CCPA 1977).
Claim 7 recites that the device is an antenna comprising at least one unit cell. Kim discloses that the device can be an antenna ([0072]). Any antenna can be considered a single unit cell. It would have been obvious to use the structure of DeLaCruz to implement an antenna, as Kim teaches forming them by stacking electronic devices over a die.
Claim 8: a wafer level chip scale package (WLCSP) and a wafer level fanout package (WLFO) are product-by-process terms; that is, they are limiting on the resulting device only as to the resulting structure. Those in the art would recognize that the structure of Kim could be formed by a wafer level process, either a WLCSP or a WLFO, depending on the relative pitches of the pads on the chip and the substrate. Those in the art would recognize that the device of Kim was or could be a wafer level chip scale package. It would have been obvious to have such in DeLaCruz as known in the art.
Claim 10: an interposer is any substrate that interposes between a chip or package and other substrate (or board, etc.). In this case substrate 19 of DeLaCruz can be considered an interposer, as it is to be mountable on a different substrate or board (See FIG. 11A). The dies and the over mold are on top surface of what it is mounted to, and the over mold would at least partially (on the top) encloses the interposer.
Claim 11: DeLaCruz discloses one or more vias (131) disposed to provide electronic connectivity between the top surface of the over mold and the top surface of the interposer without engaging the die (FIG. 11A).
Claim 14: DeLaCruz discloses
a die (145);
an over mold (143) surrounding the die;
and a plurality of vias (231) transiting a top surface of the over mold, disposed to engage electronic components (165) on the top surface and produce electronic connectivity to a top surface of the die,
wherein a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board.
The examiner understands “a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board” to mean that there are electrical contacts or pads on the bottom surface of the die. In this case, those are bottom contacts 17 of the die.
Claim 14 recites a plurality of electronic components disposed on the top surface and electrically coupled to the die through the plurality of vias, while DeLaCruz only illustrates a single device 165. However, having multiple elements would have been merely multiplication of parts. See also Kim, FIG. 1, which shows that it was known to have multiple devices connected over the die,
Claim 14 also recites that the plurality of electronic components and the plurality of vias define a conductive path between the plurality of electronic components and the die, the conductive path forming a loop area oriented entirely orthogonal to the die. DeLaCruz discloses multiple vertical vias 231 connected to the die 145. The examiner takes official notice that there will of necessity be input and output signals, and thus it there will be a current loop. Alternatively, see Cornelius, FIG. 3, which shows a current loop formed by two vias and an electronic component (capacitor 108; note that 165 of DeLaCruz can be a passive element ([0062]), of which capacitors are a very common type ([0003])). It would have been inherent or very obvious for a current loop to be formed. The area of the current loop would be determined by an input via and an output via, which are vertical, and the area defined by those vertical vias would be an area that is entirely orthogonal to the die (having a horizontal main surface).
Furthermore, DeLaCruz discloses a structure which is essentially identical to the applicant’s disclosure (FIG. 2). “Where, as here, the claimed and prior art products are identical or substantially identical, or are produced by identical or substantially identical processes, the PTO can require an applicant to prove that the prior art products do not necessarily or inherently possess the characteristics of his claimed product. See In re Ludtke, supra. Whether the rejection is based on ‘inherency’ under 35 USC 102, on ‘prima facie obviousness’ under 35 USC 103, jointly or alternatively, the burden of proof is the same, and its fairness is evidenced by the PTO's inability to manufacture products or to obtain and compare prior art products.” In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433-434 (CCPA 1977).
Claim 14 recites that this is a system comprising an antenna comprising at least one unit cell. Kim discloses that the device can be an antenna ([0072]). Any antenna can be considered a single unit cell. It would have been obvious to use the structure of DeLaCruz to implement an antenna, as Kim teaches forming them by stacking electronic devices over a die.
Claim 15: a wafer level chip scale package (WLCSP) and a wafer level fanout package (WLFO) are product-by-process terms; that is, they are limiting on the resulting device only as to the resulting structure. Those in the art would recognize that the structure of Kim could be formed by a wafer level process, either a WLCSP or a WLFO, depending on the relative pitches of the pads on the chip and the substrate. It would have been obvious to have such in DeLaCruz as known in the art.
Claim 17: an interposer is any substrate that interposes between a chip or package and other substrate (or board, etc.). In this case substrate 19 of DeLaCruz can be considered an interposer, as it is to be mounted on a substrate or circuit board. The dies 20 and the over mold are on its top surface, and the over mold at least partially (on the top) encloses the interposer.
Claim 18: DeLaCruz discloses one or more vias (131) disposed to provide electronic connectivity between the top surface of the over mold and the top surface of the interposer without engaging the die (FIG. 11A).
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over DeLaCruz in view of Kim and Panagopoulos, US 2025/0006719 A1, and in evidence or in view of Cornelius. Kim discloses that it can be an antenna ([0072]). A known configuration for an antenna consisted of unit cells; See Panagopoulos, FIG. 14, unit cells (142 and/or 104). Kim in view of Panagopoulos discloses a circuit board (Panagopoulos, 112), wherein: each unit cell is disposed on a top surface of the circuit board (Panagopoulos FIG. 14). It would have been obvious to have used such a configuration in DeLaCruz in view of Kim as a known antenna configuration.
Claims 6, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over DeLaCruz in view of Kim and Abdulla, US 2016/0197653 A1, and in evidence or in view of Cornelius. In the case of using the device of DeLaCruz in view of Kim as an antenna (Kim [0072]), it would have been obvious to have made the antenna tunable, as this was well-known in the art, and would have lead to an antenna usable at multiple frequencies. See Abdulla ([0028]): “One of the capacitances 28, in one embodiment, may be tunable so that the frequency at which the antenna transmits or receives may be altered.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is listed in the attached Notice of References Cited: Liou, US 2011/0169163 A1, which discloses device 122 over die 102 and mold 114.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER BRADFORD/Primary Examiner, Art Unit 2897
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