DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the antenna comprising a plurality of unit cells must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by DeLaCruz, US 2017/0194281 A1.
Claim 1: DeLaCruz discloses
a die (145);
an over mold (143) surrounding the die;
and a plurality of vias (231) transiting a top surface of the over mold, disposed to engage electronic components on the top surface and produce electronic connectivity to a top surface of the die (165),
wherein a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board (through interconnects 17).
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Claim 2: a wafer level chip scale package (WLCSP) and a wafer level fanout package (WLFO) are product-by-process terms; that is, they are limiting on the resulting device only as to the resulting structure. Those in the art would recognize that the structure of DeLaCruz could be formed by a WLCSP process; that is, the fan out substrate 19 could be attached to the chip while on the wafer.
Claim 3: DeLaCruz discloses an interposer (19), wherein the die and over mold are disposed on a top surface of the interposer and the over mold at least partially encloses the interposer. The substrate 19 has bonding pads on the bottom, and thus can be attached to another substrate or circuit board; thus the substrate 19 can be considered an interposer, that is, a substrate that interposes between the chip and another substrate.
Claim 4: DeLaCruz discloses one or more vias (131) disposed to provide electronic connectivity between the top surface of the over mold and the top surface of the interposer without engaging the die.
Claim 5: DeLaCruz discloses one or more electronic components (165) disposed on the top surface of the over mold, each in electronic communication with at least one of the plurality of vias (FIG. 11A).
Claims 1-5, 7, 8, 10-12, 14, 15, and 17-19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kim, US 2022/0157676 A1.
Claim 1: Kim discloses
a die (20);
an over mold (16) surrounding the die;
“During the lamination process, a portion of the first dielectric layer 16 can flow into the cavity 22 between the die 20 and the sidewall 26 of the cavity such that the portion at least partially encapsulates the die within the cavity.” [0042].
and a plurality of vias (60, [0040]) transiting a top surface of the over mold, disposed to engage electronic components (30) on the top surface and produce electronic connectivity to a top surface of the die (FIG. 3I),
wherein a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board.
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The examiner understands “a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board” to mean that there are electrical contacts or pads on the bottom surface of the die. In this case, those are bottom contacts 23 ([0040]) of the die.
Claim 2: a wafer level chip scale package (WLCSP) and a wafer level fanout package (WLFO) are product-by-process terms; that is, they are limiting on the resulting device only as to the resulting structure. Those in the art would recognize that the structure of Kim could be formed by a wafer level process, either a WLCSP or a WLFO, depending on the relative pitches of the pads on the chip and the substrate.
Claim 3: an interposer is any substrate that interposes between a chip or package and other substrate (or board, etc.). In this case substrate 18 can be considered an interposer, as it is to be mounted on a substrate or circuit board. The dies 20 and the over mold are on its top surface, and the over mold at least partially (on the top) encloses the interposer.
Claim 4: Kim discloses one or more vias (upper portion of 47) disposed to provide electronic connectivity between the top surface of the over mold and the top surface of the interposer without engaging the die. The upper portion of 47 goes from the top surface of the interposer 18 to above the top of the over mold.
Claim 5: Kim discloses one or more electronic components (30) disposed on the top surface of the over mold, each in electronic communication with at least one of the plurality of vias.
Claim 7: Kim discloses an antenna ([0072]) comprising: a plurality of unit cells, each unit cell (each individual die 20) comprising:
a die (20);
an over mold (16) surrounding the die;
and a plurality of vias (60) transiting a top surface of the over mold, disposed to engage electronic components on the top surface and produce electronic connectivity to a top surface of the die,
wherein a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board.
The examiner understands “a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board” to mean that there are electrical contacts or pads on the bottom surface of the die. In this case, those are bottom contacts 23 ([0040]) of the die.
Note that the cells (dies) need not have separate packaging to fall within the scope of claim 7.
Claim 8: a wafer level chip scale package (WLCSP) and a wafer level fanout package (WLFO) are product-by-process terms; that is, they are limiting on the resulting device only as to the resulting structure. Those in the art would recognize that the structure of Kim could be formed by a wafer level process, either a WLCSP or a WLFO, depending on the relative pitches of the pads on the chip and the substrate. Those in the art would recognize that the device of Kim was or could be a wafer level chip scale package.
Claim 10: an interposer is any substrate that interposes between a chip or package and other substrate (or board, etc.). In this case substrate 18 can be considered an interposer, as it is to be mounted on a substrate or circuit board. The dies 20 and the over mold are on its top surface, and the over mold at least partially (on the top) encloses the interposer.
Claim 11: Kim discloses one or more vias (47) disposed to provide electronic connectivity between the top surface of the over mold and the top surface of the interposer without engaging the die. The upper portion of 47 goes from the top surface of the interposer 18 to above the top of the over mold.
Claim 12: Kim discloses one or more electronic components (30) disposed on the top surface of the over mold, each in electronic communication with at least one of the plurality of vias (FIG. 1).
Claim 14: Kim discloses a system comprising an antenna ([0072]) having: a plurality of unit cells, each unit cell comprising:
a die (20);
an over mold (16) surrounding the die;
and a plurality of vias (60) transiting a top surface of the over mold, disposed to engage electronic components on the top surface and produce electronic connectivity to a top surface of the die,
wherein a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board.
The examiner understands “a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board” to mean that there are electrical contacts or pads on the bottom surface of the die. In this case, those are bottom contacts 23 ([0040]) of the die.
Claim 15: a wafer level chip scale package (WLCSP) and a wafer level fanout package (WLFO) are product-by-process terms; that is, they are limiting on the resulting device only as to the resulting structure. Those in the art would recognize that the structure of Kim could be formed by a wafer level process, either a WLCSP or a WLFO, depending on the relative pitches of the pads on the chip and the substrate.
Claim 17: an interposer is any substrate that interposes between a chip or package and other substrate (or board, etc.). In this case substrate 18 can be considered an interposer, as it is to be mounted on a substrate or circuit board. The dies 20 and the over mold are on its top surface, and the over mold at least partially (on the top) encloses the interposer.
Claim 18: Kim discloses one or more vias (47) disposed to provide electronic connectivity between the top surface of the over mold and the top surface of the interposer without engaging the die. The upper portion of 47 goes from the top surface of the interposer 18 to above the top of the over mold.
Claim 19: Kim discloses one or more electronic components (30) disposed on the top surface of the over mold, each in electronic communication with at least one of the plurality of vias.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Wu, US 20210/098421 A1.
Claim 1: Wu discloses
a die (130);
an over mold (140, [0076]) surrounding the die;
and a plurality of vias (134) transiting a top surface of the over mold, disposed to engage electronic components on the top surface and produce electronic connectivity to a top surface of the die,
wherein a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board (through conductive pattern 112).
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Claim 2: the electronic package comprises one of a lead frame package, a wafer level chip scale package (WLCSP), or a wafer level fanout package (WLFO). Wu discloses that the package may be an integrated fan-out (InFO) package ([0040]), which is a type of wafer level fanout package. Also, the device of FIG. 4B would appear to those in the art to the be a wafer level chip scale package.
Claim 3: an interposer is any substrate that interposes between a chip or package and other substrate (or board, etc.). In this case substrate 110 can be considered an interposer, as it is to be mounted on a substrate or circuit board. The die 130 and the over mold 140 are disposed on a top surface of the interposer, and the over mold at least partially (on the top) encloses the interposer.
Claim 4: Wu discloses one or more vias (120, Wu FIG. 4B) disposed to provide electronic connectivity between the top surface of the over mold and the top surface of the interposer without engaging the die.
Claim 5: Wu discloses one or more electronic components (200) disposed on the top surface of the over mold, each in electronic communication with at least one of the plurality of vias.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-12 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Panagopoulos, US 2025/0006719 A1. Kim discloses that it can be an antenna ([0072]). A known configuration for an antenna consisted of a plurality of unit cells; See Panagopoulos, FIG. 14, unit cells (142 and/or 104).
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It would have been obvious to have used such an assembly of multiple unit antenna cells in order to allow for multiple frequency communication.
Claim 7: Kim in view of Panagopoulos discloses an antenna (Kim [0072]; Panagopoulos) comprising: a plurality of unit cells, each unit cell (Panagopoulos 142) comprising (Kim FIG. 1):
a die (20);
an over mold (16) surrounding the die;
and a plurality of vias (60) transiting a top surface of the over mold, disposed to engage electronic components on the top surface and produce electronic connectivity to a top surface of the die,
wherein a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board.
The examiner understands “a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board” to mean that there are electrical contacts or pads on the bottom surface of the die. In this case, those are bottom contacts 23 ([0040]) of the die.
Claim 8: a wafer level chip scale package (WLCSP) and a wafer level fanout package (WLFO) are product-by-process terms; that is, they are limiting on the resulting device only as to the resulting structure. Those in the art would recognize that the structure of Kim could be formed by a wafer level process, either a WLCSP or a WLFO, depending on the relative pitches of the pads on the chip and the substrate. those in the art would recognize that the device of Kim was or could be a wafer level chip scale package.
Claim 9: Kim in view of Panagopoulos discloses a circuit board (Panagopoulos, 112), wherein: each unit cell is disposed on a top surface of the circuit board (Panagopoulos FIG. 14).
Claim 10: an interposer is any substrate that interposes between a chip or package and other substrate (or board, etc.). In this case substrate 18 can be considered an interposer, as it is to be mounted on a substrate or circuit board. The dies 20 and the over mold are on its top surface, and the over mold at least partially (on the top) encloses the interposer.
Claim 11: Kim discloses one or more vias (47) disposed to provide electronic connectivity between the top surface of the over mold and the top surface of the interposer without engaging the die. The upper portion of 47 goes from the top surface of the interposer 18 to above the top of the over mold.
Claim 12: Kim discloses one or more electronic components (30) disposed on the top surface of the over mold, each in electronic communication with at least one of the plurality of vias.
Claim 14: Claim 7: Kim in view of Panagopoulos discloses a system comprising an antenna (Kim [0072]; Panagopoulos) having: a plurality of unit cells, each unit cell (Panagopoulos 142) comprising (Kim FIG. 1):
a die (20);
an over mold (16) surrounding the die;
and a plurality of vias (60) transiting a top surface of the over mold, disposed to engage electronic components on the top surface and produce electronic connectivity to a top surface of the die,
wherein a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board.
The examiner understands “a bottom surface of the die is configured for electronic connectivity to an interposer or circuit board” to mean that there are electrical contacts or pads on the bottom surface of the die. In this case, those are bottom contacts 23 ([0040]) of the die.
Claim 15: a wafer level chip scale package (WLCSP) and a wafer level fanout package (WLFO) are product-by-process terms; that is, they are limiting on the resulting device only as to the resulting structure. Those in the art would recognize that the structure of Kim could be formed by a wafer level process, either a WLCSP or a WLFO, depending on the relative pitches of the pads on the chip and the substrate.
Claim 16: Kim in view of Panagopoulos discloses a circuit board (Panagopoulos 112), wherein: each unit cell is disposed on a top surface of the circuit board (FIG. 14).
Claim 17: an interposer is any substrate that interposes between a chip or package and other substrate (or board, etc.). In this case substrate 18 can be considered an interposer, as it is to be mounted on a substrate or circuit board. The dies 20 and the over mold are on its top surface, and the over mold at least partially (on the top) encloses the interposer.
Claim 18: Kim discloses one or more vias (47) disposed to provide electronic connectivity between the top surface of the over mold and the top surface of the interposer without engaging the die. The upper portion of 47 goes from the top surface of the interposer 18 to above the top of the over mold.
Claim 19: Kim discloses one or more electronic components (30) disposed on the top surface of the over mold, each in electronic communication with at least one of the plurality of vias.
Claims 6, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Abdulla, US 2016/0197653 A1. In the case of using the device of Kim as an antenna ([0072]), it would have been obvious to have made the antenna tunable, as this was well- known in the art, and would have lead to an antenna usable at multiple frequencies. See Abdulla ([0028]): “One of the capacitances 28, in one embodiment, may be tunable so that the frequency at which the antenna transmits or receives may be altered.”
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Wu ‘405, US 2015/0115405 A1.
Claim 3: an interposer is any substrate that interposes between a chip or package and other substrate (or board, etc.). In this case substrate 110 can be considered an interposer, as it is to be mounted on a substrate or circuit board. The die 130 and the over mold 140 are disposed on a top surface of the interposer, and the over mold at least partially (on the top) encloses the interposer. Alternatively, it was known to have interposers to fan out the contacts. See Wu ‘405, which shows “interposer is configured to spread the pitch between connections and/or redirect a connection to a different connection.” ([0004], FIG. 2). It would have been obvious to have had such an interposer in Wu for this purpose. As the interposer of Wu ‘405 is within the ends of the packaging substrate 206, it would have been enclosed by the over mold when incorporated into the device of Wu.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is listed in the attached Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897