Prosecution Insights
Last updated: April 19, 2026
Application No. 18/514,514

SEMICONDUCTOR DEVICE WITH 2-PHASE COOLING STRUCTURE

Non-Final OA §102
Filed
Nov 20, 2023
Examiner
SPALLA, DAVID C
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
89%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
703 granted / 836 resolved
+16.1% vs TC avg
Minimal +5% lift
Without
With
+4.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
18 currently pending
Career history
854
Total Applications
across all art units

Statute-Specific Performance

§103
47.7%
+7.7% vs TC avg
§102
34.4%
-5.6% vs TC avg
§112
8.6%
-31.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 836 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 09/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by US PG Pub 2023/0307316 to Chen et al (hereinafter Chen). Regarding Claim 1, Chen discloses a semiconductor device comprising: a semiconductor chip (10, Fig.1); a cooling channel (SC) configured to allow a coolant to (i) flow in liquid phase and (ii) absorb heat generated by the semiconductor chip during operation [0041]; and a wick structure (WS, Fig. 2) configured to generate a capillary force for moving the coolant in the liquid phase along a wall surface of the cooling channel [0043], wherein the wick structure comprises a suspended wick structure that is disposed apart from the wall surface by a capillary distance (Fig. 2). Allowable Subject Matter Claims 14-20 are allowed. Claims 2-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: Claim 14 recites a semiconductor device comprising: a semiconductor chip; a supply channel disposed on an upper surface of the semiconductor chip that is configured to move a coolant in liquid phase along the upper surface of the semiconductor chip by capillary action; a cooling channel formed by recessing the upper surface of the semiconductor chip, the cooling channel comprising: a bottom that is parallel to the upper surface and a side wall that connects the upper surface of the semiconductor chip and the bottom to each other; and a first wick structure disposed apart from the side wall of the cooling channel that is configured to supply the coolant in the liquid phase to the bottom of the cooling channel along the side wall of the cooling channel by capillary action. Chen does not disclose the wick structure as having been formed by recessing the upper surface of the semiconductor chip. US PG Pub 2024/0194565 (“Kollipara”) and US PG Pub 2023/0223318 (“Wu”) are cited as being examples of relevant references in the art for comparison to Applicant’s invention. The references form channels for coolant, including free standing wicks, by recessing a surface of the semiconductor chip or die. However, the references do not form the channels or wicks such that a capillary action occurs to cool the chip. While the process or function of cooling the chip may not be relevant to the structure, by claiming the need for capillary action, Applicant infers a channel size and distance for the wicks to be spaced apart from the sidewalls. The references of record do not disclose or suggest such distances. A search of other, relevant references does not show Applicant’s invention to be anticipated or obvious. Claims 15-20 depend on Claim 14 and are allowable for at least the reasons above. For similar reasons, Claims 2-6 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 7 and 10 require a supply opening or coolant storage portion to accommodate coolant in the liquid phase and supply the liquid to the wick structure. Chen’s wick structure appears to be self contained and relies on capillary action to circulate the liquid. Chen does not disclose a storage or supply channel in a manner as claimed by Applicant. Claims 8-9 and 11-12 depend on Claims 7 and 10, respectively, and are allowable for at least the reasons above. Claim 13 requires a stack of semiconductor chips having cooling channels and a connection channel penetrating therethrough in the vertical direction wherein a connection wick structure is disposed on at least a portion of a wall surface of the connection channel that is configured to move the coolant in the liquid phase by generating a second capillary force. Such a stacked assembly and shared channel structure between the chips is not an obvious modification of the references of record. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID C SPALLA/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Nov 20, 2023
Application Filed
Jan 10, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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SEMICONDUCTOR DEVICE HAVING SIDE SPACER PATTERNS
2y 5m to grant Granted Apr 14, 2026
Patent 12593475
FIELD EFFECT TRANSISTOR WITH ISOLATION STRUCTURE AND METHOD
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Patent 12588233
SEMICONDUCTOR DEVICE HAVING U-SHAPED STRUCTURE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12586644
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2y 5m to grant Granted Mar 24, 2026
Patent 12581677
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2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
89%
With Interview (+4.7%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 836 resolved cases by this examiner. Grant probability derived from career allow rate.

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