DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species 3 in the reply filed on 3/27/2026 is acknowledged.
Claims 3, 4, and 10-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/27/2026.
Note: Applicants indicated claims 5 and 19 as withdrawn. This appears to be erroneous as elected species 3 relates to compressed laminates. As such, claims 5 and 19 will remain and claim 3 has been withdrawn since it is drawn to non-elected species 1 (compressed fiberglass strands).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US PG Pub 2023/0384682, hereinafter Wang) in view of KONISHI et al. (US PG Pub 2017/0221786, hereinafter Konishi).
Regarding claim 1, figure 2B of Wang discloses a semiconductor device assembly, comprising:
a semiconductor die (200) comprising:
a substrate (201) having:
an insulator portion (part of the SOI, ¶ 26); and
a semiconductive portion (silicon portion of SOI, ¶ 26) adhered directly to the insulator portion;
a layer of dielectric material (205) disposed at the semiconductive portion; and
circuitry (203, ¶ 29) disposed at the layer of dielectric material.
Wang does not explicitly disclose the insulator portion is an engineered portion including one or more of: a sintered material, a corrugated material, oriented strands of material compressed to form a solid structure, layers of material compressed to form a solid structure, and a material arranged to form one or more planar trusses
In the same field of endeavor, figure 1F of Konishi discloses an SOI substrate comprises:
a substrate having:
an engineered portion (1/2) including a sintered material (1, ¶ 42); and
a semiconductive portion (4a) adhered directly to the engineered portion.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the insulator portion of Wang to be an engineered portion as taught by Konishi for the purpose of reducing contamination during manufacturing (¶ 14).
Regarding claim 2, figure 1F of Konishi discloses the engineered portion (1/2) is thicker than the semiconductive portion (4a).
Regarding claim 8, the prior art does not explicitly disclose a package-level substrate; and an additional semiconductor die, wherein the additional semiconductor die is mounted to the semiconductor die, and wherein the semiconductor die and the additional semiconductor die are electrically coupled to the package-level substrate.
However, the claimed elements are well-known in the art and it would have been obvious to form the die of Wang on a package level substrate along with an additional die mounted thereon and couple them to the package-level substrate for the purpose of forming a high density memory device.
Regarding claim 9, figure 1F of Konishi discloses the engineered portion (1/2) includes a non-crystalline material (2, ¶ 42).
Allowable Subject Matter
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-20 are allowed.
Regarding claim 15, the closest prior art of record, KONISHI et al. (US PG Pub 2017/0221786), either singularly or in combination, does not disclose or suggest the combination of limitations including “a semiconductor device substrate, comprising:
a semiconductive portion; and
an engineered portion including:
a first portion that includes one or more of: sintered material, layers of material compressed to form a solid structure, and oriented strands of material compressed into a solid structure; and
a second portion disposed between the first portion and the semiconductive portion and directly adhered to the semiconductive portion, the second portion including one or more of: a corrugated material and a material arranged to form one or more planar trusses”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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