DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 in the reply filed on 5/11/26 is acknowledged.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Gutala et al (US 2018/0211900).
1. (Original) A semiconductor device assembly, comprising:
a substrate (Fig.1 (107) and [0015]);
a semiconductor die (Fig.1 (103/104/105) and [0015]) assembled onto the substrate (Fig.1 (107) and [0015]);
a layer of dielectric material (Fig.1/3 (102/302) and [0014- carrier die/0017/0028]) disposed on a back surface of the semiconductor die (Fig.1/3 (102/302) and [0017/0028]), the layer of dielectric material (Fig.1/3 (102/302) and [0017/0028]) defining a channel (Fig.1 (1-8/11-17/27-30) and [0017]) configured to enable a fluid [0017] to flow through the channel (Fig.1 (1-8/11-17/27-30) and [0017]) and cause heat to be transferred from the semiconductor die to the fluid through the back surface of the semiconductor die [0017-0019], the layer of dielectric material (Fig.1/3 (102/302) and [0017/0028]) including a plurality of structures [0024- smaller pitch=greater flow rate] extending through the channel (Fig.1 (1-8/11-17/27-30) and [0017]) effective to accelerate a flow of the fluid through the channel (Fig.1 (1-8/11-17/27-30) and [0017]) [0024- smaller pitch=greater flow rate];
an inlet (Fig.1 (111) and [0017]) configured to receive the fluid to be flowed through the channel; and
an outlet (Fig.1 (112) and [0017]) configured to expel the fluid after it has been flowed through the channel (Fig.1 (1-8/11-17/27-30) and [0017]).
It is implicit and/or obvious that the fluid routing device (Fig.1/3 (102/302) and [0017/0028]) is made of a dielectric material. Gutala [0014] teaches the channels are located within a carrier die. One of ordinary skill in the art would recognize the carrier dies is likely to be monocryalline silicon/ glass or silicon carbide- all dielectric materials well known for their suitable thermal conductivity properties.
2. (Original) The semiconductor device assembly of claim 1, further comprising: an additional semiconductor die (Fig.1 (103/104/105) and [0015]) assembled onto the substrate (Fig.1 (107) and [0015]); and an additional layer of dielectric material (Fig.1/3 (102/302) and [0017/0028]) disposed on a back surface of the additional semiconductor die (Fig.1 (103/104/105) and [0015]), the additional layer of dielectric material (Fig.1/3 (102/302) and [0017/0028]) defining an additional channel (Fig.1 (1-8/11-17/27-30) and [0017]) configured to enable additional fluid to flow through the additional channel (Fig.1 (1-8/11-17/27-30) and [0017]) and cause heat to be transferred from the additional semiconductor die (Fig.1 (103/104/105) and [0015]) to the additional fluid through the back surface of the additional semiconductor die (Fig.1 (103/104/105) and [0015]), wherein the inlet (Fig.1 (111) and [0017]) is configured to receive the additional fluid to be flowed through the additional channel (Fig.1 (1-8/11-17/27-30) and [0017]), and wherein the outlet (Fig.1 (112) and [0017]) is configured to receive the additional fluid after it has been flowed through the additional channel (Fig.1 (1-8/11-17/27-30) and [0017]).
3. (Original) The semiconductor device assembly of claim 2, further comprising: an input channel (Fig.1 (1-8/11-17/27-30) and [0017]) configured to: transport the fluid from the inlet (Fig.1 (111) and [0017]) to the channel (Fig.1 (1-8/11-17/27-30) and [0017]); and transport the additional fluid from the inlet (Fig.1 (111) and [0017]) to the additional channel (Fig.1 (1-8/11-17/27-30) and [0017]); and an output channel (Fig.1 (1-8/11-17/27-30) and [0017]) configured to: transport the fluid from the channel (Fig.1 (1-8/11-17/27-30) and [0017]) to the outlet (Fig.1 (112) and [0017]); and transport the additional fluid from the additional channel (Fig.1 (1-8/11-17/27-30) and [0017]) to the outlet (Fig.1 (112) and [0017]).
4. (Original) The semiconductor device assembly of claim 3, further comprising another layer of dielectric material (Fig.1/3 (102/302) and [0017/0028]) disposed at the substrate (Fig.1 (107) and [0015]) between the semiconductor die (Fig.1 (103/104/105) and [0015]) and the additional semiconductor die (Fig.1 (103/104/105) and [0015]), the other layer of dielectric material (Fig.1/3 (102/302) and [0017/0028]) defining the input channel and the output channel (Fig.1 (1-8/11-17/27-30) and [0017]).
5. (Original) The semiconductor device assembly of claim 1, wherein the plurality of structures are disposed in a grid [Fig.1/3 (102/302) [0024- smaller pitch-grid].
6. (Original) The semiconductor device assembly of claim 1, wherein the channel (Fig.1/3 (1-8/11-17/27-30) and [0017]) is enclosed by a lid [0014] that is supported by the plurality of structures [Fig.1/3 (102/302) [0024- smaller pitch-grid]..
7. (Original) The semiconductor device assembly of claim 6, wherein: the inlet (Fig.1 (111) and [0017]) is configured to receive the fluid through a first opening in the lid [0014]; and the outlet (Fig.1 (112) and [0017]) is configured to expel the fluid through a second opening in the lid [0014].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gutala et al (US 2018/0211900).
Gutala teaches the limitations of claim 6 above; however fails to explicitly teach wherein the lid comprises silicon nitride as required in claim 8 below:
8. (Original) The semiconductor device assembly of claim 6, wherein the lid comprises silicon nitride.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Gutala’s teachings to form the lid from silicon nitride because silicon nitride is a commonly used material for thermal interface materials.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gutala et al (US 20170133298); Brunschwiler et al (US 20170179001); and Leobandung et al (US 20190385928) teach similar channel cooling structures for chip devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
6/23/26
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