DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDSs) submitted on 11/20/23, 7/30/24 and 1/15/25 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 19-24, 26, and 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al., US 2018/0190740 in view of Kumagai, US 2007/0263164. Regarding claim 1, Bang teaches (at least in Figure 4) a display panel comprising: a base layer (111) ; a first anode (261) disposed on the base layer; a pixel defining layer (271 and 272) disposed on the base layer, wherein the pixel defining layer is provided with a first light emitting opening (P1, P2, P3) which exposes at least a portion of the first anode; a partition wall (274, 273) disposed on the pixel defining layer, wherein the partition wall is provided with a first partition wall opening corresponding to the first light emitting opening (id at Figure 4) ; a first cathode (263) at least partially disposed in the first partition wall opening (see Figure 4) and disposed over the anode (id) ; and a first emission pattern (262) disposed between the anode and the first cathode. Bang is silent as to a first conductive pattern being formed directly on the first anode. However, in the same field of endeavor of OLEDs, Kumagai teaches a first conductive pattern disposed in the first light emitting opening and disposed on the first anode; wherein the first conductive pattern contacts a side surface of the pixel defining layer which defines the first light emitting opening ([0064] and Figure 8B, anode 15a and conductive oxide layer 15b) . Further, it was well known to those of ordinary skill in the art at the time of filing that a stacked structure comprising a reflective anode and conductive oxide structure would improve light emission efficiency of an OLED device. Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing to provide the Bang device with a first conductive pattern disposed directly on the anode layer in order to improve light emission efficiency. Regarding claim 2, Bang and Kumagai teach the invention as explained above regarding claim 1, and Bang further teaches the pixel defining layer includes: a lower insulating layer (271, see Figure 4) including a first insulating material (id); and an upper insulating layer (272) including a second insulating material (id) different from the first insulating material ([0072]), wherein the upper insulating layer is disposed on the lower insulating layer (see Figure 4). Regarding claim 3, Bang and Kumagai teach the invention as explained above regarding claim 2, and Bang further teaches the lower insulating layer (271, Figure 4) includes a lower inner surface which defines a first lower region of the first light emitting opening (part recessed further away from center of opening than 272) , wherein the upper insulating layer includes an upper inner surface which defines a first upper region of the first light emitting opening (272, see Figure 4) , and wherein the lower inner surface is disposed to be recessed in a direction away from a center of the first anode with respect to the upper inner surface (see Figure 4) . Regarding claim 4, Bang and Kumagai teach the invention as explained above regarding claim 3, and Bang further teaches the lower insulating layer (271) contacts and upper surface of the first anode (see Figure 4, 271 contacts upper surface of anode 261). Further, based on the combined teaching and structure of Bang and Kumagai, the first conductive layer would have also contacted an inner surface of the lower insulating layer. Regarding claim 19, Bang and Kumagai teach the invention as explained above regarding claim 2, and Bang further teaches the first insulating material and second insulating material may be different from each other ([0072]). Bang also teaches an alternating layer stack of silicon nitride and silicon oxide are effective insulators ([0054]). Therefore, it is the position of the examiner that although the reference does not specifically teach the two insulating layers having the claimed material, it would have been obvious for one of ordinary skill in the art at the time of filing to utilize the same based on their well-known insulating qualities. Regarding claim 20, Bang and Kumagai teach the invention as explained above regarding claim 2, and further it is the position of the examiner that lacking criticality and unexpected results, it would have been an obvious matter of routine experimentation and design choice for one of ordinary skill in the art to optimize the relative thickness of each insulating layer to appropriately separate the pixels while ensuring maximum light emission efficiency. Regarding claim 21, Bang and Kumagai teach the invention as explained above regarding claim 1, but Bang is silent as to the material of the first conductive layer. Kumagai , however, further teaches the first conductive pattern includes a same material as a material included in the first anode ([0123], the electrode may be formed of a single layer or a dual layer, therefore they may be formed of the same material) . Further, it was well known to those of ordinary skill in the art at the time of filing that a stacked structure comprising a reflective anode and conductive oxide structure would improve light emission efficiency of an OLED device. Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing to provide the Bang device with a first conductive pattern disposed directly on the anode layer in order to improve light emission efficiency. Regarding claim 22, Bang and Kumagai teach the invention as explained above regarding claim 1, but Bang is silent as to the material of the first conductive layer. Kumagai , however, further teaches the first conductive pattern includes transparent conductive oxide ([0120]) . Further, it was well known to those of ordinary skill in the art at the time of filing that a stacked structure comprising a reflective anode and conductive oxide structure would improve light emission efficiency of an OLED device. Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing to provide the Bang device with a first conductive pattern disposed directly on the anode layer in order to improve light emission efficiency. Regarding claim 23, Bang and Kumagai teach the invention as explained above regarding claim 1, and further it is the position of the examiner that lacking criticality and unexpected results, it would have been an obvious matter of routine experimentation and design choice for one of ordinary skill in the art to optimize the relative thickness of each first conductive pattern to appropriately illuminate the pixels while ensuring maximum light emission efficiency and display thinness. Regarding claim 24, Bang teaches a display panel (Figure 4) comprising: a base layer (111); an anode (261) disposed on the base layer; a lower insulating layer (271) disposed on the base layer, wherein the lower insulating layer is provided with a lower opening (see P1, P2, P3) defined therein to expose a portion of the anode; an upper insulating layer (272) disposed on the lower insulating layer, wherein the upper insulating layer is provided with an upper opening defined therein to correspond to the lower opening (see Figure 4); a partition wall (274 and 273) disposed on the upper insulating layer, wherein the partition wall is provided with a partition wall opening defined therein to correspond to the upper opening (see Figure 4); a cathode (263) at least partially disposed in the partition wall opening; and an emission pattern (262) disposed between the conductive pattern and the cathode, wherein on a section, the upper opening has a smaller width in one direction than the lower opening (see Figure 4, opening created by 272 is smaller than opening created by 271). Bang is silent as to a first conductive pattern being formed directly on the first anode. However, in the same field of endeavor of OLEDs, Kumagai teaches a first conductive pattern disposed in the first light emitting opening and disposed on the first anode; wherein the first conductive pattern contacts a side surface of the pixel defining layer which defines the first light emitting opening ([0064] and Figure 8B, anode 15a and conductive oxide layer 15b). Further, it was well known to those of ordinary skill in the art at the time of filing that a stacked structure comprising a reflective anode and conductive oxide structure would improve light emission efficiency of an OLED device. Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing to provide the Bang device with a first conductive pattern disposed directly on the anode layer in order to improve light emission efficiency. Regarding claim 26, Bang teaches a method for manufacturing a display panel, the method comprising: providing a preliminary display panel (Figure 4) including a base layer (111) and a first anode (261) disposed on the base layer; forming, on the base layer, a preliminary pixel defining layer (271 and 272) including a lower insulating layer (271) including a first insulating material ([0072]) and an upper insulating layer (272) including a second insulating material different from the first insulating layer ([0072]) ; forming a preliminary partition wall (274 and 273) on the preliminary pixel defining layer; patterning the preliminary partition wall to form a partition wall with a first partition wall opening defined therein ([0106]) ; patterning the preliminary pixel defining layer to form a pixel defining layer with a first light emitting opening defined therein to expose at least a portion of the first anode ([0108]) ; forming a first emission pattern (262) on the first conductive pattern; and forming a first cathode (263) on the first emission pattern, wherein the first cathode is at least partially disposed in the first partition wall opening (see Figure 4) . Bang is silent as to a first conductive pattern being formed directly on the first anode. However, in the same field of endeavor of OLEDs, Kumagai teaches a first conductive pattern disposed in the first light emitting opening and disposed on the first anode; wherein the first conductive pattern contacts a side surface of the pixel defining layer which defines the first light emitting opening ([0064] and Figure 8B, anode 15a and conductive oxide layer 15b). Further, it was well known to those of ordinary skill in the art at the time of filing that a stacked structure comprising a reflective anode and conductive oxide structure would improve light emission efficiency of an OLED device. Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing to provide the Bang device with a first conductive pattern disposed directly on the anode layer in order to improve light emission efficiency. Regarding claim 30, Bang and Kumagai teach the invention as explained above regarding claim 26, and Bang further teaches in the forming the first conductive pattern, a first dummy pattern and a second preliminary dummy pattern are additionally formed, wherein the first dummy pattern is spaced apart from the first conductive pattern and disposed in the first light emitting opening and the first partition wall opening, and the second preliminary dummy pattern is spaced apart from the first conductive pattern and the first dummy pattern and includes one portion disposed on the partition wall and a remaining portion disposed in the first partition wall opening (see [0105-0108]) . Regarding claim 31, Bang and Kumagai teach the invention as explained above regarding claim 30, and Bang further teaches patterning the second preliminary dummy pattern to form a second dummy pattern after the forming the first conductive pattern and before the forming the first emission pattern ([0105-0108 and [0112]) , wherein in the providing the preliminary display panel, the preliminary display panel further includes a second anode spaced apart from the first anode and disposed on the base layer (see Figure 4, anode in each of P1, P2, P3) , and wherein the patterning the second preliminary dummy pattern includes removing a portion of the second preliminary dummy pattern overlapping the second anode ([0105-0108]) . Regarding claim 32, Bang and Kumagai teach the invention as explained above regarding claim 31, and Bang further teaches forming, in the partition wall, a second partition wall (273) opening to overlap the second anode after the forming the first cathode (P1, P2, P3) ; forming, in the pixel defining layer, a second light emitting opening to expose at least a portion of the second anode (Figure 4, see P1, P2, P3, so P2 has second light emitting opening) ; forming a second emission pattern (262 in P2) on the second conductive pattern; and forming, on the second emission pattern, a second cathode (263) at least partially disposed in the second partition wall opening. Bang is silent as to a first conductive pattern being formed directly on the first anode. However, in the same field of endeavor of OLEDs, Kumagai teaches a first conductive pattern disposed in the first light emitting opening and disposed on the first anode; wherein the first conductive pattern contacts a side surface of the pixel defining layer which defines the first light emitting opening ([0064] and Figure 8B, anode 15a and conductive oxide layer 15b). Further, it was well known to those of ordinary skill in the art at the time of filing that a stacked structure comprising a reflective anode and conductive oxide structure would improve light emission efficiency of an OLED device. Therefore, it would have been obvious for one of ordinary skill in the art at the time of filing to provide the Bang device with a first conductive pattern disposed directly on the anode layer in order to improve light emission efficiency. Allowable Subject Matter Claims 5-18, 25, and 27-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or suggest a first and second partition wall layer wherein the first partition wall inner surface is disposed to be recessed in the direction away from the center of the first anode with respect to the upper inner surface and the second partition wall inner surface, in combination with the remaining limitations of claim 5. Further, the prior art fails to teach or suggest a first additional insulating layer disposed between the base layer and the lower insulating layer, wherein the first additional insulating layer is disposed to be recessed in the direction away from the center of the first anode with respect to the upper inner surface and the second additional inner surface, in conjunction with the remaining limitations of claim 16. Further, the prior art fails to teach or suggest a first and second partition wall, wherein the remaining region of the partition wall opening has a smaller width in the one direction than the one region of the partition wall opening, in conjunction with the remaining limitations of claim 25. Further, the prior art fails to teach or suggest patterning the preliminary partition wall includes performing a first etching process and second etching process, and an etch rate of the first partition wall is higher than an etch rate of the second partition wall layer in conjunction with the remaining limitations of claim 27. Further, the prior art fails to teach or suggest in performing the third etching process, an etch rate of the lower insulating layer is higher than an etch rate of the upper insulating layer in conjunction with the remaining limitations of claim 28. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Choung et al., US 11348983 teaches an OLED comprising a pixel defining layer comprised of two different material layers, as well as a partition formed on the pixel defining layer. Choung fails to teach the first material layer of the pixel defining layer is recessed away from the center of the opening with respect to the second material layer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MARY-ELLEN BOWMAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-5383 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Thursday; 7:00 am-5:00 pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. FILLIN "Examiner Stamp" \* MERGEFORMAT MARY ELLEN BOWMAN Examiner Art Unit 2875 /MARY ELLEN BOWMAN/ Primary Examiner, Art Unit 2875