Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 04/13/2026. Currently, claims 1-23 are pending in the application. Claims 11-15 have been withdrawn from consideration.
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-10 and 16-23, in the reply filed on 04/13/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10, 16-18 and 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HO et al (KR 20210037950 A). A machine English translation of HO is attached with this office action.
Regarding claim 1, Figures 9/11 of HO disclose an organic light-emitting diode display device, comprising:
a plurality of sub-pixels (SP1/SP2/SP3, Page 21 of English translation) disposed on a substrate (100);
at least one transistor (250) disposed at each of the plurality sub-pixels over the substrate;
a first insulation (200) layer disposed over the at least one transistor; and
a light-emitting diode (at 700) disposed at each of the plurality of sub-pixels over the first insulation layer, the light-emitting diode including a first electrode (310), a light-emitting layer (700), and a second electrode (800), wherein each of the plurality of sub-pixels includes a contact area (on top of 250) and an emission area (at 700), wherein the light-emitting diode is electrically connected to the at least one transistor in the contact area, and wherein the first insulation layer (200) includes a recessed portion (for CH layers) in the contact area.
Regarding claim 2, Figures 9/11 of HO disclose that the organic light-emitting diode display device of claim 1, further comprising: at least one contact electrode (411) and at least one reflection layer (315, Figure 9) disposed on a same layer between the first insulation layer (200) and the light-emitting diode (at 700), the at least one contact electrode and at least one reflection layer including a same material (Page 8 of English translation), wherein the at least one contact electrode (411) is disposed in the contact area, and the at least one reflection layer (315) is disposed in the emission area.
Regarding claim 3, Figures 9/11 of HO disclose that the organic light-emitting diode display device of claim 2, wherein the at least one contact electrode (411) is disposed in the recessed portion of the first insulation layer (200), and wherein a distance between the at least one contact electrode and the substrate is shorter than a distance between the at least one reflection layer and the substrate (411 is in the recess and the 315 on 200, so the distance is shorter with the substrate than the distance between 315 and 100).
Regarding claim 4, Figures 9/11 of HO disclose that the organic light-emitting diode display device of claim 1, further comprising: first, second, and third reflection layers (315/325/335, Page 11, English translation) disposed in the emission area between the first insulation layer (200) and the light-emitting diode (at 700), wherein the plurality of sub-pixels include first, second, and third sub-pixels, and wherein the first, second, and third reflection layers are disposed in the first, second, and third sub-pixels, respectively (please see Figure 9).
Regarding claim 5, Figures 9/11 of HO disclose that the organic light-emitting diode display device of claim 4, wherein a distance between the second reflection layer (325) and the second electrode (800) in the second sub-pixel (SP2) is smaller than a distance between the first reflection layer (315) and the second electrode (800) in the first sub-pixel (SP1), and wherein the distance between the second reflection layer (325) and the second electrode (800) in the second sub-pixel (SP2) is greater than a distance between the third reflection layer (325) and the second electrode (800) in the third sub-pixel (SP3).
Regarding claim 6, Figures 9/11 of HO disclose that the organic light-emitting diode display device of claim 4, further comprising: second (510) and third (520) insulation layers disposed between the first insulation layer (200) and the light-emitting diode (at 700), wherein the first reflection layer (315) is disposed between the first (200) and second (510) insulation layers in the first sub-pixel (SP1), the second reflection layer (325) is disposed between the second (510) and third (520) insulation layers in the second sub-pixel (SP2), and the third reflection layer (335) is disposed between the third insulation layer (520) and the light-emitting diode (at 7800) in the third sub-pixel (SP3).
Regarding claim 7, Figures 9/11 of HO disclose that the organic light-emitting diode display device of claim 6, further comprising: first (411), second (412), and third (413) contact electrodes disposed in the contact area of each of the first, second, and third sub-pixels, wherein the first, second, and third contact electrodes overlap with each other in the contact area and are electrically connected to each other, and wherein the first, second, and third contact electrodes overlap with the recessed portion (CH11/CH21/CH31) of the first insulation layer (200).
Regarding claim 8, Figures 9/11 of HO disclose that the organic light-emitting diode display device of claim 7, wherein the first contact electrode (411) is disposed between the first (200) and second (510) insulation layers, wherein the second contact electrode (412) is disposed between the second (510) and third (520) insulation layers, and wherein the third contact electrode (413) is disposed between the third insulation layer (520) and the light-emitting diode.
Regarding claim 9, Figures 9/11 of HO disclose that the organic light-emitting diode display device of claim 1, further comprising: a bank (600) disposed between the first electrode (310) and the light-emitting layer (700), the bank (600) covering edges of the first electrode and exposing a central portion of the first electrode, wherein the bank is disposed in the contact area (please see Figure 11).
Regarding claim 10, Figures 9/11 of HO disclose that the organic light-emitting diode display device of claim 9, further comprising: a trench (T) disposed in the bank (600) in an area between adjacent sub-pixels among the plurality of sub-pixels.
Regarding claim 16, Figures 9/11 of HO disclose a display device, comprising:
a first sub-pixel (SP1, Page 17 in the English translation), a second sub-pixel (SP2) and a third sub-pixel (SP3) disposed on a substrate (100);
a first transistor (250 at CH11), a second transistor (250 at CH21) and a third transistor (250 at CH31) disposed on the substrate and corresponding to the first sub-pixel, the second sub-pixel and the third sub-pixel, respectively;
a first light emitting element (at 700, under 910) disposed in the first sub-pixel, a second light emitting element (at 700, under 920) disposed in the second sub-pixel and a third light emitting element (at 700, under 930) disposed in the third sub-pixel;
a first insulation layer (200) disposed on the first transistor, the second transistor and the third transistor; and
a first reflection layer (315) disposed in the first sub-pixel, a second reflection layer (325) disposed in the second sub-pixel, and a third reflection layer (335) disposed in the third sub-pixel, wherein the first insulation layer (200, Page 17 in the English translation) includes a first-first recessed portion (at CH11) in the first sub-pixel, a first-second recessed portion (at CH21) in the second sub-pixel and a first-third recessed portion (at CH31) in the third sub-pixel.
Regarding claim 17, Figures 9/11 of HO disclose that the display device of claim 16, wherein the first reflection layer (315) is located a first distance away from the first light emitting element, the second reflection layer (325) is located a second distance away from the second light emitting element, and the third reflection layer (335) is located a third distance away from the third light emitting element, and wherein the first distance is greater than the second distance, and the second distance is greater than the third distance (please see Figure 9).
Regarding claim 18, Figures 9/11 of HO disclose that the display device of claim 16, wherein an upper end of the first reflection layer (315) overlaps with the first light emitting element (at 700) and a lower end of the first reflection layer overlaps with the first-first recessed portion in the first insulation layer (when 315 is formed with the first contact electrode 411, page 8 in the English translation), wherein an upper end of the second reflection layer (325) overlaps with the second light emitting element and a lower end of the second reflection layer overlaps with the first-second recessed portion in the first insulation layer (200) (Page 11 of English translation), and wherein an upper end of the third reflection layer (315) overlaps with the third light emitting element and a lower end of the third reflection layer overlaps with the first-third recessed portion in the first insulation layer (considering 335 is formed with upper electrode 413, Page 11 of English translation).
Regarding claim 20, Figures 9/11 of HO disclose that the display device of claim 16, further comprising: a trench (T) disposed between two adjacent sub-pixels among the first, second and third sub-pixels, wherein at least one layer in two light emitting elements in the two adjacent sub-pixels is disconnected or cut in an area overlapping with the trench (T).
Regarding claim 21, Figures 9/11 of HO disclose that the display device of claim 16, further comprising: a second insulation layer (510) disposed on the first insulation layer; and a third insulation layer (520) disposed on the second insulation layer, wherein the first reflection layer (315) of the first sub-pixel is disposed between the first insulation layer and the second insulation layer, wherein the second reflection layer (325) of the second sub-pixel is disposed between the second insulation layer (520) and the third insulation layer (530), and wherein the third reflection layer (335) of the third sub-pixel is disposed between the third insulation layer (530) and the third light emitting element (under 930).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being obvious over HO et al (KR 20210037950 A) in view of IM et al (US 20210202651 A1).
Regarding claim 19, Figures 9/11 of HO do not teach that the display device of claim 16, wherein the first reflection layer (315) is electrically connected to the first transistor, wherein the second reflection layer (325) is electrically connected to the second transistor, and wherein the third reflection layer (335) is electrically connected to the third transistor.
However, IM is a pertinent art which teaches a display device, wherein Figure 5 of IM teaches that the reflection layers (RP1/RP2/RP3) are connected to the transistors (31/32/33) ([0049]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of HO, wherein the first reflection layer (315) is electrically connected to the first transistor, wherein the second reflection layer (325) is electrically connected to the second transistor, and wherein the third reflection layer (335) is electrically connected to the third transistor (250) according to the teaching of IM in order to have the ease of fabrication and reduce cost.
Claim 23 is rejected under 35 U.S.C. 103 as being obvious over HO et al (KR 20210037950 A) in view of Lee et al (US 20200235172 A1).
Regarding claim 23, Figures 9/11 of HO do not teach that the display device of claim 16, wherein the first-first recessed portion in the first insulation layer does not overlap with a first emission area of the first light emitting element, wherein the first-second recessed portion in the first insulation layer does not overlap with a second emission area of the second light emitting element, and wherein the first-third recessed portion in the first insulation layer does not overlap with a third emission area of the third light emitting element.
However, Lee is a pertinent art which teaches a display device, wherein Figure 7 teaches that the transistor (120) connecting the light emitting diode is located in the non-emission area ([0129]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the display device of HO, wherein the first-first recessed portion in the first insulation layer does not overlap with a first emission area of the first light emitting element, wherein the first-second recessed portion in the first insulation layer does not overlap with a second emission area of the second light emitting element, and wherein the first-third recessed portion in the first insulation layer does not overlap with a third emission area of the third light emitting element according to the teaching of Lee in order to have a display device with improved luminosity ([0143] of Lee).
Allowable Subject Matter
Claim 22 is objected to as being dependent upon rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 22, there is no prior art available nor obvious motivation to combine elements of prior art which teaches a display device: comprising: “a second-first recessed portion in the second insulation layer in the first sub-pixel, a second-second recessed portion in the second insulation layer in the second sub-pixel, and a second-third recessed portion in the second insulation layer in the third sub-pixel; and a third-first recessed portion in the third insulation layer in the first sub-pixel, a third-second recessed portion in the third insulation layer in the second sub-pixel, and a third-third recessed portion in the third insulation layer in the third sub-pixel, wherein the first-first recessed portion, the second-first recessed portion and the third-first recessed portion overlap with each other in the first sub-pixel, wherein the first-second recessed portion, the second-second recessed portion and the third-second recessed portion overlap with each other in the second sub-pixel, and wherein the first-third recessed portion, the second-third recessed portion and the third-third recessed portion overlap with each other in the third sub-pixel” in combination with other limitations of the claim it depends on.
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice .
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAJA AHMAD/Primary Examiner, Art Unit 2813