DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
3. Claim(s) 1-20, is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al., US 2007/0132365 A1.
Claims 1, 17, 20. Kang et al., disclose a display apparatus (such as the one in fig. 3, [0035], [0043], [0049]), comprising:
-a substrate (item 31) including an active area and a non-active area having a pad unit (active layer 41 of the thin film transistor 40, [0038]);
-a thin film transistor (item 40) disposed in the active area;
-a light emitting diode (item 52 disposed in the active area and connected to the thin film transistor;
-an encapsulation layer (item 37) covering the thin film transistor and the light emitting diode;
-a touch electrode array (item 51) disposed in the active area on the encapsulation layer;
-a first touch pad electrode (item 412/413) disposed in the pad unit of the substrate and connected to the touch electrode array through a touch link line (this limitation would read through [0067] wherein is disclosed in FIG. 3, a bus line 70 may be disposed in contact with the second electrode 53. The bus line 70, formed together with the source and drain electrodes 43 and 44, also has a first conductive layer 701, a second conductive layer 702, and a third conductive layer 703);
-and a planarization film (item 46, [0080]) which is patterned in the pad unit to cover a part of the first touch pad electrode (this limitation would read through [0080] wherein is disclosed a planarization layer 46 is formed on the substrate including the source and drain electrodes 43 and 44 and the interconnection 80 to complete a TFT panel).
Kang appears to not specify that the planarization film is patterned in the pad unit in an island shape. However, [0081] of Kang indicates for example, the planarization layer 46 is formed, and then patterned to form a via-hole 36 exposing a portion of one of the source and drain electrodes 43 and 44, for example, the drain electrode 44. Here, while the via-hole 36 is formed, a passivation layer pattern 81 having an opening 81a exposing a portion of the interconnection 80 and disposed on a side end of the interconnection 80 is simultaneously formed. The Applicant has not presented persuasive evidence that the claimed shape is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed shape). Also, the applicant has not shown that the claimed island shape produces a result that was new or unexpected enough to patent-ably distinguish the claimed invention over the cited prior art. It has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (in re Aller); similarly, it is not inventive to discover the optimum shape by routine experimentation (In re Dailey, 357 F.2d 869, 149 USPQ 47 (CCPA 1966); in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984); MPEP 2144.04).
Claims 2-5. Kang et al., disclose the display apparatus according to claim 1, further comprising: a first pad unit line and a second pad unit line disposed in the pad unit of the substrate, wherein the first pad unit line and the second pad unit line are disposed on a same layer as a gate electrode of the thin film transistor and a gate line (this limitation would read through [0039] wherein is disclosed the gate electrode 42 is disposed on the gate insulating layer 33, and an interlayer insulating layer 34 is formed to cover the gate electrode 42. In addition, a source electrode 43 and a drain electrode 44 are disposed on the interlayer insulating layer 34, and then a passivation layer (or a passivation layer pattern) 35 is disposed to cover the source and drain electrodes 43 and 44).
Claims 6-8. Kang et al., disclose the display apparatus according to claim 5, further comprising: a first display pad electrode disposed on a same layer as the first touch pad electrode in the pad unit, wherein the first touch pad electrode is disposed on the interlayer insulating film in the pad unit to be connected to the first pad unit line through the first pad unit contact hole, and the first display pad electrode is disposed on the interlayer insulating film in the pad unit to be connected to the second pad unit line through the second pad unit contact hole (this limitation would read through [0067] wherein is disclosed the source and drain electrodes 43 and 44 are formed, various conductors including the interconnection 60 in the pixel may be formed. For example, as shown in FIG. 3, a bus line 70 may be disposed in contact with the second electrode 53. The bus line 70, formed together with the source and drain electrodes 43 and 44, also has a first conductive layer 701, a second conductive layer 702, and a third conductive layer 703. The first, second and third conductive layers 701, 702 and 703 may be formed of the same materials as the conductive layer materials. The bus line 70 is in contact with the second electrode 53 through a via-hole 39 formed in the passivation layer 35 to allow power to be supplied to the second electrode 53).
Claims 9-11. Kang et al., disclose the display apparatus according to claim 8, further comprising: a touch buffer film disposed on the encapsulation layer, wherein the touch electrode array is configured by a plurality of first touch electrodes and a plurality of second touch electrodes intersecting each other, and the touch buffer film is located between the first touch electrode and the second touch electrode and the touch link line and the encapsulation layer (this limitation would read through [0037] wherein is disclosed an insulating layer 32 such as a barrier layer and/or a buffer layer may be formed on the substrate 31 to prevent (or reduce) diffusion of impurity ions and penetration of moisture or external air, and to planarize a surface thereof).
Claims 12-16, 18-19. Kang et al., disclose the display apparatus according to claim 10, further comprising: a touch insulting film disposed on the touch link line, wherein the touch insulating film is removed from the pad unit to be spaced apart from one end of the planarization film which is patterned in the pad unit in an island shape with a predetermined distance, so as to be open, and the touch insulting film is spaced apart from one ends of the touch link line and the touch buffer film with a predetermined distance (this limitation would read through [0076] wherein is disclosed after forming the source and drain regions 412 and 413 in the active layer 41, an interlayer insulating layer 34 is formed on the entire surface of the substrate, including the active layer 41, and contact holes are formed to expose a portion of the source and drain regions 412 and 413 in the interlayer insulating layer 34).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899