DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/10/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-11 & 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cao (US 20070170444) in view of Fan et al. (US 20090078955) and further in view of Koyama et al. (US 20130065331).
Regarding claim 1, Cao discloses that a light emitting device, comprising:
a substrate 301 (Fig. 3);
a first semiconductor layer 305-308 disposed on the substrate 301;
a second semiconductor layer 312-316 disposed on the first semiconductor layer 305-308 (Fig. 3);
a third semiconductor layer 320-324 disposed on the second semiconductor layer 312-316 (Fig. 3); and
a plurality of connection electrodes 309, 317, 325, 326, 318, 310 electrically connected to at least one of the first, the second, and the third semiconductor layers, wherein the plurality of connection electrodes 309, 317, 325, 326, 318, 310 overlap a region of at least one of the first, the second, and the third semiconductor layers, wherein at least one of the plurality of connection electrodes includes a first region that extends toward a center of at least one of the first, the second, and the third semiconductor layers and a second region that extends toward an outside away from the center (Fig. 3, an each electrode 309, 317, 325, 326, 318, 310 has a thickness and extending from a center of semiconductor layer to an outside away from the center), wherein a first connection electrode 310 of the plurality of connection electrodes includes a first terminal 310 disposed on the substrate and a second terminal 309 disposed opposite to the first terminal (Fig. 3).
Cao fails to teach that wherein the first terminal and the second terminal are a part of a same single electrode, which is the first connection electrode, which is the first connection electrode, and a surface area of the first terminal is greater than a surface area of the second terminal and the second terminal disposed opposite to the first terminal in a direction parallel to a top surface of the substrate.
However, Fan suggests that the first terminal 224 and the second terminal 226 are a part of a same single electrode 230 (Fig. 2B).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Cao with the first terminal and the second terminal are a part of a same single electrode, which is the first connection electrode, which is the first connection electrode as taught by Fan in order to enhance connectivity, less electrical connections, and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Cao & Fan fail to teach that a surface area of the first terminal is greater than a surface area of the second terminal and the second terminal disposed opposite to the first terminal in a direction parallel to a top surface of the substrate.
PNG
media_image1.png
545
1001
media_image1.png
Greyscale
Koyama suggests that a surface area of the first terminal 11 is greater than a surface area of the second terminal 12 and the second terminal 12 disposed opposite to the first terminal 11 in a direction parallel to a top surface of the substrate 1 (Fig. 1).
PNG
media_image2.png
501
883
media_image2.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Cao & Fan with a surface area of the first terminal is greater than a surface area of the second terminal disposed opposite to the first terminal in a direction parallel to a top surface of the substrate as taught by Koyama in order to enhance a bonding strength and to reduce a contact resistance (para. 0060) and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 2, Cao, Fan & Koyama disclose that the first region 325 is disposes on the third semiconductor layer 321-324 and the second region overlaps at least one side surface of the first, the second, and the third semiconductor layers (Cao’s Fig. 3 in view of Koyama Fig. 1).
Reclaim 3, Cao , Fan & Koyama disclose that a length of the first region is different from a length of the second region (Fig. 3, Cao).
Reclaim 4, Cao, Fan & Koyama disclose that a length of the second region is longer than a length of the first region (a length from other side of third LED).
Reclaim 5, Cao, Fan & Koyama fail to specify that a difference between a length of the first region and a length of the second region is about 25%.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain difference between a length of the first region and a length of the second region, because it would have been to obtain a certain difference between a length of the first region and a length of the second region to achieve controlling current delivery.
Reclaim 6, Cao, Fan & Koyama disclose that an insulation layer 327 configured to cover a region of the first, the second, and the third semiconductor layers (Cao, Fig. 3).
Reclaim 7, Cao, Fan & Koyama fail to specify that a region of the insulation layer has a thickness of less than about 100 um.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of an insulating layer, because it would have been to obtain a certain thickness of the insulating layer to achieve protection from outer damage or suitable electrical damage.
Reclaim 8, Cao, Fan & Koyama disclose that the substrate includes a circuit pattern that is electrically connected to at least one of the first, the second, and the third semiconductor layer (Fig. 3, Cao).
Regarding claim 9, Cao, Fan & Koyama disclose that a light emitting device, comprising:
a substrate 301 ;
a first semiconductor layer 304-308 disposed on the substrate;
a second semiconductor layer 312- 316 disposed on the first semiconductor layer;
a third semiconductor layer 320-324 disposed on the second semiconductor layer; and
a plurality of connection electrodes 309, 317, 325, 326, 318, 310 electrically connected to at least one of the first, the second, and the third semiconductor layers, wherein the plurality of connection electrodes overlap a region of at least one of the first, the second, and the third semiconductor layers, wherein at least one of the plurality of connection electrodes includes a first region that extends toward a center of at least one of the first, the second, and the third semiconductor layers and a second region that extends toward an outside away from the center 325, and wherein the first region is disposed on the third semiconductor layer and the second region overlaps at least one side surface of the first, the second, and the third semiconductor layers, and wherein a length of the first region is different from a length of the second region (Fig. 1 in view of Koyama), wherein a first connection electrode of the plurality of connection electrodes includes a first terminal 11 disposed on the substrate and the second terminal 12 disposed opposite to the first terminal in a direction parallel to a top surface of the substrate 1 (Koyama, Fig. 1), wherein the first terminal and the second terminal are a part of a same single electrode, which is the first connection electrode (Cao in view of Fan’s 2A).
Reclaim 10, Cao, Fan & Koyama disclose that the length of the second region is longer than the length of the first region (Cao Fig. 3 in view of Koyama’s Fig. 1).
Reclaim 11, Cao, Fan & Koyama fail to specify that a difference between the length of the first region and the length of the second region is about 25%.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain difference between a length of the first region and a length of the second region, because it would have been to obtain a certain difference between a length of the first region and a length of the second region to achieve controlling current delivery.
Reclaim 13, Cao, Fan & Koyama disclose that an area of a surface of the first terminal is greater than an area of a surface of the second terminal.
Reclaim 14, Cao, Fan & Koyama disclose that an insulation layer 327 configured to cover a region of the first, the second, and the third semiconductor layers (Cao in view of Koyama).
Cao, Fan & Koyama fail to specify that a region of the insulation layer has a thickness of less than about 100 um.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of an insulating layer, because it would have been to obtain a certain thickness of the insulating layer to achieve protection from outer damage or suitable electrical damage.
Regarding claim 15, Cao, Fan & Koyama disclose that a light emitting device, comprising:
a substrate 301;
a first semiconductor layer 304-308 disposed on the substrate;
a second semiconductor layer 312-316 disposed on the first semiconductor layer;
a third semiconductor layer 320-324 disposed on the second semiconductor layer; and
a plurality of connection electrodes electrically connected to at least one of the first, the second, and the third semiconductor layers, wherein the plurality of connection electrodes overlap a region of at least one of the first, the second, and the third semiconductor layers, wherein at least one of the plurality of connection electrodes includes a first region that extends toward a center of at least one of the first, the second, and the third semiconductor layers and a second region that extends toward an outside away from the center, wherein a first connection electrode 310 of the plurality of connection electrodes includes a first terminal electrically connected to the first semiconductor layer and a second terminal disposed opposite to the first terminal, wherein the first terminal and the second terminal are a part of a same single electrode, which is the first connection electrode (Cao in view of Fan’s Fig. 2A), and wherein a surface area of the first terminal 11 is greater than a surface area of the second terminal 12 (Fig. 3 in view of Koyama Fig. 1) and the second terminal 110b or 201b disposed opposite to the first terminal in a direction parallel to a top surface of the substrate 200 (Fig. 3 in view of Koyama Fig. 1).
Reclaim 16, Cao, Fan & Koyama disclose that the first region is disposed on the third semiconductor layer and the second region overlaps at least one side surface of the first, the second, and the third semiconductor layers (Fig. 3 in view of Koyama Fig. 1).
Reclaim 17, Cao, Fan & Koyama disclose that a length of the first region is different from a length of the second region (Fig. 3 in view of Koyama Fig. 1).
Reclaim 18, Cao, Fan & Koyama disclose that a length of the second region is longer than a length of the first region (Fig. 3 in view of Koyama Fig. 1).
Reclaim 19, Cao, Fan & Koyama fail to specify that a difference between a length of the first region and a length of the second region is about 25%.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain difference between a length of the first region and a length of the second region, because it would have been to obtain a certain difference between a length of the first region and a length of the second region to achieve controlling current delivery.
Reclaim 20, Cao, Fan & Koyama disclose that an insulation layer configured to cover a region of the first, the second, and the third semiconductor layers.
Cao, Fan & Koyama fail to specify that a region of the insulation layer has a thickness of less than about 100 um.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of an insulating layer, because it would have been to obtain a certain thickness of the insulating layer to achieve protection from outer damage or suitable electrical damage.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-11 & 13-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 11855121 in view of Cao and further in view of Fan & Koyama et al.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SU C KIM/Primary Examiner, Art Unit 2899
Prosecution Insights