DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-11 & 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanbayashi (US 20040155326) in view of Yoon et al. (US 20140312369) and further in view of Koyama et al. (US 20130065331).
Regarding claim 1, Kanbayashi discloses that a light emitting device, comprising:
a substrate 10;
a first semiconductor layer 20 disposed on the substrate 10;
a second semiconductor layer 30 disposed on the first semiconductor layer 20;
a third semiconductor layer 40 disposed on the second semiconductor layer 30 (Fig. 1); and
a plurality of connection electrodes 50 electrically connected to at least one of the first 20 , the second 30, and the third semiconductor layers 40, wherein the plurality of connection electrodes overlap a region of at least one of the first 20, the second 30, and the third semiconductor layers 40, wherein at least one of the plurality of connection electrodes 50 includes a first region that extends toward a center of at least one of the first 20, the second, 30 and the third semiconductor layers 40 and a second region that extends toward an outside away from the center (Fig. 1 & 2), wherein a first connection electrode of the plurality of connection electrodes includes a first terminal 16 disposed on the substrate 10 and a second terminal 22 disposed opposite to the first terminal 16 in a direction parallel to a top surface of the substrate 10 (some portion of element 16 are parallel to a top surface of substrate 10), which is the first connection electrode, wherein the first connection electrode includes a connecting portion 50 that connects the first terminal 16 and the second terminal 22 , and the connecting portion 50 is diagonally inclined between the first terminal and the second terminal (some portion of connecting portion 50 is diagonally inclined between the first terminal and the second terminal 22).
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Kanbayashi fails to specify that the first terminal and the second terminal are a part of a same single electrode and wherein a surface area of the first terminal is greater than a surface area of the second terminal.
However, Yoon suggests that terminal 130 can be single electrode (para. 0050).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Kanbayashi with the first terminal and the second terminal are a part of a same single electrode, which is the first connection electrode, which is the first connection electrode as taught by Yoon in order to enhance connectivity, less electrical connections, and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Kanbayashi & Yoon fail to teach that a surface area of the first terminal is greater than a surface area of the second terminal and the second terminal disposed opposite to the first terminal in a direction parallel to a top surface of the substrate.
Koyama suggests that a surface area of the first terminal 11 is greater than a surface area of the second terminal 12 and the second terminal 12 disposed opposite to the first terminal 11 in a direction parallel to a top surface of the substrate 1 (Fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Kanbayashi & Yoon with a surface area of the first terminal is greater than a surface area of the second terminal disposed opposite to the first terminal in a direction parallel to a top surface of the substrate as taught by Koyama in order to enhance a bonding strength and to reduce a contact resistance (para. 0060) and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 2, Kanbayashi & Yoon, & Koyama disclose that the first region is disposed on the third semiconductor layer and the second region overlaps at least one side surface of the first, the second, and the third semiconductor layers (Kanbayashi, Fig. 1-2).
Reclaim 3, Kanbayashi & Yoon, & Koyama disclose that a length of the first region is different from a length of the second region (Kanbayashi, Fig. 1-2).
Reclaim 4, Kanbayashi & Yoon, & Koyama disclose that a length of the second region is longer than a length of the first region (Kanbayashi, Fig. 1-2).
Reclaim 5, Kanbayashi & Yoon, & Koyama disclose that a difference between a length of the first region and a length of the second region is about 25%. (Kanbayashi, Fig. 1-2, it is matter of how to define a first region and second region).
Reclaim 6, Kanbayashi & Yoon, & Koyama disclose that an insulation layer configured to cover a region of the first, the second, and the third semiconductor layers (Kanbayashi, Fig. 1-2, it is matter of how to define a first region and second region).
Reclaim 7, Kanbayashi & Yoon, & Koyama fail to specify that a region of the insulation layer has a thickness of less than about 100 um.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of an insulating layer, because it would have been to obtain a certain thickness of the insulating layer to achieve protection from outer damage or suitable electrical damage.
Reclaim 8, Kanbayashi & Yoon, & Koyama disclose that the substrate includes a circuit pattern that is electrically connected to at least one of the first, the second, and the third semiconductor layer (Kanbayashi, Fig. 1).
Regarding claim 9, Kanbayashi & Yoon, & Koyama disclose that a light emitting device, comprising:
a substrate 10 (Kanbayashi, Fig. 1-2);
a first semiconductor layer 20 disposed on the substrate 10;
a second semiconductor layer 30 disposed on the first semiconductor layer 20;
a third semiconductor layer 40 disposed on the second semiconductor layer 30; and
a plurality of connection electrodes 50 electrically connected to at least one of the first 20, the second 30, and the third semiconductor layers 40, wherein the plurality of connection electrodes 50 overlap a region of at least one of the first 20, the second 30, and the third semiconductor layers 40, wherein at least one of the plurality of connection electrodes includes a first region that extends toward a center of at least one of the first, the second, and the third semiconductor layers and a second region that extends toward an outside away from the center (from left to right in Fig. 1), wherein the first region is disposed on the third semiconductor layer and the second region overlaps at least one side surface of the first, the second, and the third semiconductor layers, wherein a length of the first region is different from a length of the second region (Kanbayashi, Fig. 1-2), wherein a first connection electrode of the plurality of connection electrodes includes a first terminal 18 disposed on the substrate 10 and a second terminal 22 disposed opposite to the first terminal in a direction parallel to a top surface of the substrate 10, [[and]] wherein the first terminal and the second terminal are a part of a same single electrode (Yoon, para. 0050), which is the first connection electrode and wherein the first connection electrode includes a connecting portion 50 that connects the first terminal 18 and the second terminal 22, and the connecting portion is diagonally inclined between the first terminal and the second terminal (some portion of connecting portion is diagonally inclined in Kobayashi’s Fig. 1).
Reclaim 10, Kanbayashi & Yoon, & Koyama disclose that the length of the second region is longer than the length of the first region.
Reclaim 11, Kanbayashi & Yoon, & Koyama disclose that a difference between the length of the first region and the length of the second region is about 25% (Kanbayashi. Fig. 1, it is matter how to define a first region).
Reclaim 13, Kanbayashi & Yoon, & Koyama disclose that an area of a surface of the first terminal is greater than an area of a surface of the second terminal (Koyama, Fig. 1a-c).
Reclaim 14, Kanbayashi & Yoon, & Koyama disclose that an insulation layer configured to cover a region of the first, the second, and the third semiconductor layers (Kanbayashi. Fig. 1).
Kanbayashi & Yoon, & Koyama fails to specify that a region of the insulation layer has a thickness of less than about 100 um.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of an insulating layer, because it would have been to obtain a certain thickness of the insulating layer to achieve protection from outer damage or suitable electrical damage.
Regarding claim 15, Kanbayashi & Yoon, & Koyama disclose that a light emitting device, comprising:
a substrate 10 (Kanbayashi. Fig. 1);
a first semiconductor layer20 disposed on the substrate;
a second semiconductor layer 30 disposed on the first semiconductor layer;
a third semiconductor layer 40 disposed on the second semiconductor layer; and
a plurality of connection electrodes 50 electrically connected to at least one of the first, the second, and the third semiconductor layers, wherein the plurality of connection electrodes 50 overlap a region of at least one of the first 20, the second 30, and the third semiconductor layers 40, wherein at least one of the plurality of connection electrodes 50 includes a first region that extends toward a center of at least one of the first, the second, and the third semiconductor layers and a second region that extends toward an outside away from the center, wherein a first connection electrode of the plurality of connection electrodes includes a first terminal 22 electrically connected to the first semiconductor layer 20 and a second terminal 32 disposed opposite to the first terminal in a direction parallel to a top surface of the substrate, wherein the first terminal 22 and the second terminal 33 (Kanbayashi. Fig. 1) are a part of a same single electrode (Yoon, para. 0050), which is the first connection electrode 22, wherein the first connection electrode 50 includes a connecting portion 50 that connects the first terminal 22 and the second terminal 33, and the connecting portion is diagonally inclined (some portion is diagonally inclined in Kanbayashi’s Fig. 1) between the first terminal 22 and the second terminal 32, and wherein a surface area of the first terminal is greater than a surface area of the second terminal (Koyama, Fig. 1a-c).
Reclaim 16, Kanbayashi & Yoon, & Koyama disclose that the first region is disposed on the third semiconductor layer and the second region overlaps at least one side surface of the first, the second, and the third semiconductor layers (Fig. 1, Kanbayashi).
Reclaim 17, Kanbayashi & Yoon, & Koyama disclose that a length of the first region is different from a length of the second region (Fig. 1, Kanbayashi).
Reclaim 18, Kanbayashi & Yoon, & Koyama disclose that a length of the second region is longer than a length of the first region (Fig. 1, Kanbayashi).
Reclaim 19, Kanbayashi & Yoon, & Koyama fail to specify that a difference between a length of the first region and a length of the second region is about 25% (Kanbayashi. Fig. 1, it is matter how to define a first region).11
Reclaim 20, Kanbayashi & Yoon, & Koyama disclose that an insulation layer configured to cover a region of the first, the second, and the third semiconductor layers
Kanbayashi & Yoon, & Koyama fail to specify that a region of the insulation layer has a thickness of less than about 100 um.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain thickness of an insulating layer, because it would have been to obtain a certain thickness of the insulating layer to achieve protection from outer damage or suitable electrical damage.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
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/SU C KIM/Primary Examiner, Art Unit 2899
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