DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled in on 07/07/2026. Claims 1-16 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 01/04/2024.
Oath/Declaration
The oath or declaration filed on 11/21/2023 is acceptable.
Election/Restrictions
Applicant’s election, without traverse, species V (Fig. [4-5]) of claims 1-5 and 8-16, in the “Response to Election / Restriction Filed” filed on 07/15/2026 is acknowledged. This office action considers claims 1-16 are thus pending for prosecution of which, non-elected claims 6-7 are withdrawn, and elected claims 1-5 and 8-16 are examined on their merits.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “each of the top and bottom ends having a corresponding area; wherein the area of the top end of the first region of the cell plug is greater than the area of bottom end of the second region of the cell plug, and wherein the top end of the second region of the cell plug has an area greater than the area of the bottom end of the third region.” as recites in claim 1, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 and 8-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding Claim 1, The instant claims recite limitation “each of the top and bottom ends having a corresponding area; wherein the area of the top end of the first region of the cell plug is greater than the area of bottom end of the second region of the cell plug, and wherein the top end of the second region of the cell plug has an area greater than the area of the bottom end of the third region” is not clear the area meant by entire region or width or length is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claims 2-5 and 8-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, because of their dependency status from claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-10 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheon et al (US 2021/0151452 A1; hereafter Cheon).
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Annotated Fig [6A].
Regarding claim 1. Cheon discloses a semiconductor memory device (Fig [6A/6B]), comprising:
a gate stack (Fig [6A/6B], [ SSa. SSb], as gate stack, Para [ 0031-0032, 0054-0056]) comprising a first sub-stack (Fig [6A], annotated first sub-stack, Para [ 0031-0032, 0054-0056]), a second sub-stack (Fig [6A], annotated second sub-stack, Para [ 0031-0032, 0054-0056]), and a third sub- stack (Fig [6A], annotated third sub-stack, Para [ 0031-0032, 0054-0056]), the first to third sub-stacks being stacked on top of each other in a first direction (Fig [6A] , [ SSa. SSb], as gate stack, Para [0031-0032, 0054-0056]; and
a cell plug (Fig [6A], channel structure 130, Para [ 0037]) extending in the first direction and penetrating the first sub-stack, the second sub-stack, and the third sub-stack (Fig [6A], annotated first to third sub-stack, Para [ 0031-0032, 0054-0056]), wherein the cell plug (Fig [6A], channel structure 130, Para [ 0037]) comprises a first region (Fig [6A], upper region of channel structure 130, Para [ 0037]) penetrating the first sub-stack (annotated first sub-stack, Para [ 0031-0032, 0054-0056]), a second region (middle region of channel structure 130, Para [ 0037]) penetrating the second sub-stack (Fig [6A], annotated second sub-stack, Para [ 0031-0032, 0054-0056]), and a third region (Fig [6A], lower region of channel structure 130, Para [ 0037]) penetrating the third sub-stack (Fig [6A], annotated third sub-stack, Para [ 0031-0032, 0054-0056]), each of the first, second and third regions (upper/middle/lower region of channel structure 130, Para [ 0037]) having top and bottom ends, each of the top and bottom ends having a corresponding area (Fig [6A], upper/middle/lower region of channel structure 130, Para [ 0037]);
wherein the area of the top end of the first region of the cell plug is greater than the area of bottom end of the second region of the cell plug (Fig [6A], upper/middle region of channel structure 130, Para [ 0037]), and wherein the top end of the second region of the cell plug has an area greater than the area of the bottom end of the third region (Fig [6A], middle/lower region of channel structure 130, Para [ 0037]).
Regarding claim 2. Cheon discloses the semiconductor memory device of claim 1, Cheon further discloses wherein a length of the second region of the cell plug in the first direction (Fig [6A], middle region of channel structure 130, Para [ 0037]) is less than a length of each of the first and third regions of the cell plug in the first direction (Fig [6A], upper/lower region of channel structure 130, Para [ 0037]).
Regarding claim 3. Cheon discloses the semiconductor memory device of claim 1, Cheon further discloses wherein a sidewall slope of the second region of the cell plug (Fig [6A], middle region of channel structure 130, Para [0037]) is steeper than a sidewall slope of each of the first and third regions of the cell plug (upper/lower region of channel structure 130, Para [0037]).
Regarding claim 4. Cheon discloses the semiconductor memory device of claim 1, Cheon further discloses wherein the first sub-stack (Fig [6A], annotated first sub-stack, Para [ 0031-0032, 0054-0056]) comprises a plurality of first conductive layers (Fig [6A], G1/G2, Para [0055-0056]) and a plurality of first interlayer insulating layers ( IL1/IL2, Para [0055-0056]) stacked alternately with each other in the first direction ( Para [0055-0056]), wherein the second sub-stack (annotated second sub-stack, Para [ 0031-0032, 0054-0056]) comprises a second conductive layer (Fig [6A], DGL1/DgL2, Para [ 0031-0036]) and a second interlayer insulating layer (IL4/Il5), which are stacked in the first direction, and wherein the third sub-stack (annotated third sub-stack, Para [ 0031-0032, 0054-0056]) comprises a plurality of third conductive layers (Fig [6A], G3/G4, Para [0031-0036, 0055-0056]) and a plurality of third interlayer insulating layers (IL7/IL8, Para [0031-0036, 0055-0056]), which are stacked alternately with each other in the first direction ( Fig 6).
Regarding claim 8. Cheon discloses the semiconductor memory device of claim 1, Cheon further discloses wherein a height of the second sub-stack (annotated second sub-stack, Para [ 0031-0032, 0054-0056]) in the first direction is less than a height of each of the first (Fig [6A], annotated first sub-stack, Para [ 0031-0032, 0054-0056])and third sub-stacks in the first direction (Fig [6A], annotated third sub-stack, Para [ 0031-0032, 0054-0056]).
Regarding claim 9. Cheon discloses the semiconductor memory device of claim 1, Cheon further discloses wherein the first region of the cell plug protrudes toward a side portion 20 nm or less than the second region of the cell plug (Fig [6A], horizontal regions 130P2’, Para [0089]).
Regarding claim 10. Cheon discloses the semiconductor memory device of claim 1, Cheon further discloses wherein the second region of the cell plug protrudes toward a side portion 20 nm or less than the third region (Fig [6A], horizontal regions 130P2’, Para [0089]).
Regarding claim 12. Cheon discloses the semiconductor memory device of claim 1, wherein the cell plug comprises:
a channel structure (Fig [6A], channel structure 130, Para [ 0037]) including a first channel pillar (left channel filling layer 133, Para [ 0072]) and a second channel pillar (Fig [6A], right channel filling layer 133, Para [ 0072]) extending from the first region to the third region (annotated first to third sub-stack, Para [ 0031-0032, 0054-0056]); and a memory layer ( layers [131,132], construed as memory layer) located between the gate stack (Fig [6A], SSa/SSb, Para [0031, 0054-0056]]) and each of the first channel pillar (Fig [6A], left channel filling layer 133, Para [ 0072]) and the second channel pillar (Fig [6A], right channel filling layer 133, Para [ 0072]), and wherein the first channel pillar (Fig [6A], left channel filling layer 133, Para [ 0072]) and the second channel pillar (right channel filling layer 133, Para [ 0072]) are spaced apart from each other.
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Regarding claim 13. Cheon discloses a semiconductor memory device, comprising:
a gate stack (Fig [6A/6B], SSa/SSb, Para [0031, 0054-0056]]) comprising a plurality of conductive layers (GL1 to GL4, Para [0035]) spaced apart and stacked on each other in a first direction;
a hole extending (channel hole CHHb, as shown in Figure 8H, Para [0070-0071]) in the first direction and penetrating the plurality of conductive layers (GL1 to GL4, Para [0035]);
a channel structure (channel structure 130) comprising a first channel pillar (left channel filling layer 133, Para [ 0072]) and a second channel pillar ( right filling layer 133, Para [ 0072]) extending in the first direction, the channel structures (channel structure 130) being located in the hole (channel hole CHHb, as shown in Figure 8H, Para [ 0070-0071]) and spaced apart from each other in a second direction, the second direction lying in a plane substantially parallel with the plurality of conductive layers (GL1 to GL6, Para [ 0035]); and
a memory layer ( layers [131,132], construed as memory layer) located between the gate stack (Fig 6, SSa/SSb, Para [0031, 0054-0056]]) and each of the first channel pillar (left channel filling layer 133, Para [ 0072]) and the second channel pillar (right channel filling layer 133, Para [ 0072]), wherein a curved portion defining an undercut region (horizontal regions CHR1’, CHR2’, shows curve portion ) is formed on a sidewall of the hole, wherein the undercut region (horizontal regions CHR1’, CHR2’, shows curve portion ) comprises a first portion in the second direction (horizontal regions 130P1’, shows curve portion, Para [ 0089] ) and a second portion (horizontal regions 130P2’, shows curve portion, Para [ 0089] ) in a third direction crossing the second direction in the plane ( Fig [6A/6B]), and wherein the channel structure covers (Fig [6A/6B], channel structure 130) the first portion (Fig [6A/6B], horizontal regions 130P1’, shows curve portion, Para [ 0089] ) of the undercut region (Fig [6A/6B], horizontal regions CHR1’, CHR2’, shows curve portion ) and opens the second portion (Fig [6A/6B], horizontal regions 130P2’, shows curve portion, Para [ 0089] ) of the undercut region (Fig [6A/6B], horizontal regions CHR1’, CHR2’, shows curve portion ).
Regarding claim 14. Cheon discloses the semiconductor memory device of claim 13, Cheon further discloses wherein the second portion (Fig [6A/6B], horizontal regions 130P2’, shows curve portion, Para [0089]) of the undercut region (Fig [6A/6B], horizontal regions CHR1’, CHR2’, shows curve portion) has a width of 20 nm or less (horizontal regions 130P2’, Para [0089]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Cheon et al (US 2021/0151452 A1; hereafter Cheon).
Regarding claim 15. Cheon discloses the semiconductor memory device of claim 13, Cheon further discloses wherein the hole extends to a first width in the second direction and a second width in the third direction (channel hole CHHb, as shown in Figure 8H, Para [0070-0071]).
But Cheon does not disclose explicitly, and wherein the first width is greater than the second width.
However, Cheong discloses “each of the protrusion length d1′ of the first protrusion 130p1′ of the channel structure 130′ in the horizontal direction (X direction) and the protrusion length d2′ of the second protrusion 130p2′ of the channel structure 130′ in the horizontal direction (X direction) may be greater than 0 nm and may be less than or equal to about 10 nm”, Para [ 0089]. Based on the variation of the length, X direction, first width can greater than the second width.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Cheong width for further advantage such as high integration of memory devices.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Cheon et al (US 2021/0151452 A1; hereafter Cheon) as applied claims above and further in view of WOO et al (US 2021/0183885 A1; hereafter WOO).
Regarding claim 16. Cheon discloses the semiconductor memory device of claim 13, But Cheon discloses does not disclose explicitly wherein in the plane, the hole has an elliptical horizontal cross section having a major axis aligned with the second direction.
In a similar field of endeavor, WOO discloses wherein in the plane, the hole has an elliptical horizontal cross section having a major axis aligned with the second direction (Fig [ 3-6], Para [0049-0053])”.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Cheon in light of WOO teaching “wherein in the plane, the hole has an elliptical horizontal cross section having a major axis aligned with the second direction (Fig [ 3-6], Para [0049-0053])” for further advantage such driving NAND flash memory cell array on the peripheral circuit region and improve device performance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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