DETAILED ACTION
This Office action is in response to the election filed 11 March 2026. Claims 1-16 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-8, in the reply filed on 11 March 2026 is acknowledged.
Claims 9-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11 March 2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "an N-type drift region" in line 17; an “N-type drift region” is already positively recited in line 3 of the claim, thus it is unclear whether the limitation of line 17 is intended to refer to the previously recited “N-type drift region” of line 3 or to another, different region. For the purposes of examination, and consistent with the specification, it is assumed the above limitation of line 17 is intended to refer to --an area of the N-type drift region-- (referring to the N-type drift region recited in line 3).
Claims 2-8 depend directly or indirectly from claim 1 and thus also contain the above indefinite language.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over CN 109119468 A to Gao et al. (citations refer to the English machine translation attached; hereinafter “Gao”) in view of US 10,332,992 B1 to Kondo (hereinafter “Kondo”).
Regarding independent claim 1, as best understood, Gao (Fig. 2) discloses a semiconductor device comprising:
a drain electrode 1 (p. 4, last para.); a semiconductor layer 3/4/5/6 including an N-type drift region 3 (p. 4, last para.; p. 5, para. 4) on the drain electrode, a P-type channel region 4 (p. 4, last para.; p. 5, para. 4) on the N-type drift region, and an N-type source region 6 (p. 4, last para.; p. 5, para. 4) on the P-type channel region;
a source contact electrode 5 (p. 4, last para.; p. 5, para. 4) on the N-type source region;
an opening (7/8/9/10/11/12 disposed therein) provided in the semiconductor layer, the opening extending from the N-type source region 6 to the N-type drift region 3 (Fig. 2);
a field plate electrode 9 (p. 4, last para.; p. 5, para. 4) that is adjacent to the N-type drift region 3 arranged in the opening with an insulating film 12/11/10 (p. 4, last para.) interposed between the field plate electrode 9 and the N-type drift region 3 and is connected to a source potential (p. 5, para. 4);
a gate electrode 7 (p. 4, last para.; p. 5, para. 4) adjacent to the P-type channel region 4 arranged in the opening with the insulating film 12/11/10 interposed between the gate electrode 7 and the P-type channel region 4; and
a floating electrode 8 (p. 4, last para.; p. 5, para. 4) adjacent to an N-type drift region between the N-type drift region 3 adjacent to the field plate electrode 9 arranged in the opening and the P-type channel region 4 with the insulating film 12/11/10 interposed between the floating electrode 8 and the N-type drift region 3, wherein, when a thickness of the insulating film 12/11/10 between the field plate electrode 9 and the N-type drift region 3 is T.sub.1, a thickness of the insulating film 12/11/10 between the floating electrode 8 and the N-type drift region 3 is T.sub.2, and a thickness of the insulating film between the gate electrode 7 and the P-type channel region 4 is T.sub.3, a relationship of T.sub.1>T.sub.2 is satisfied (Fig. 2).
However, Gao fails to expressly disclose that T.sub.2>T.sub.3. In the same field of endeavor, Kondo (Fig. 2A) discloses a semiconductor device including a thickness of an insulating film 108 (col. 4, l. 36) between a gate electrode 110 (col. 4, l. 31) and an interface between the drift region 104 (col. 4, l. 35) is larger than a thickness of the insulating film 108 between a gate electrode 110 and a channel region 100 (col. 4, l. 39). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the above relationship of thicknesses, i.e. T.sub.2>T.sub.3, for the purpose of improving breakdown characteristics of the insulating layer, thus improving performance of the semiconductor device (Kondo, col. 6, ll. 18-40).
Regarding claim 2, Gao and Kondo disclose the semiconductor device according to claim 1, wherein the floating electrode 8 is provided around the field plate electrode 9 (Gao, Fig. 2).
Regarding claim 3, Gao and Kondo disclose the semiconductor device according to claim 2, wherein the field plate electrode 9 penetrates the floating electrode 8 and is adjacent to the gate electrode 7 (Gao, Fig. 2).
Regarding claim 6, Gao and Kondo disclose the semiconductor device according to claim 1, however fail to expressly disclose: wherein the floating electrode is divided into a plurality of floating electrodes, and at least one of the plurality of floating electrodes satisfies a relationship of T.sub.1>T.sub.2>T.sub.3, where T.sub.2 is a thickness of the insulating film between the one floating electrode and the N-type drift region.
Gao does disclose various configurations of floating electrode 8 (Figs. 2, 4), and discloses that a rectangular floating gate electrode 8 (Fig. 4) simplifies manufacturing and reduces switching loss (Gao, p. 5, last para.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the floating electrode of Gao and Kondo to provide a plurality of floating electrodes since the courts have held that mere duplication of parts has no patentable significance unless a new or unexpected result is produced see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Further, in view of the teachings of Kondo, it also would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the recited relationship of thicknesses for the purpose of improving breakdown characteristics of the insulating layer, thus improving performance of the semiconductor device (Kondo, col. 6, ll. 18-40).
Claims 4 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Gao and Kondo as applied to claim 1 above, and further in view of US 8,884,362 B2 to Matsuoka et al. (hereinafter “Matsuoka”).
Regarding claim 4, Gao and Kondo disclose the semiconductor device according to claim 1, however fail to expressly disclose: wherein the insulating film contains silicon oxide.
In the same field of endeavor, Matsuoka discloses the use of silicon oxide to form insulating films in semiconductor devices (col. 4, ll. 20-22). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide silicon oxide as the insulating film of Gao and Kondo for the purpose of utilizing an art recognized material known to be suitable for use in insulating films (as exemplified by Matsuoka at col. 4, ll. 20-22).
Regarding claim 7, Gao and Kondo disclose the semiconductor device according to claim 1, however fail to expressly disclose: wherein the gate electrode, the floating electrode, and the field plate electrode contain N-type polysilicon.
In the same field of endeavor, Matsuoka discloses the use of N-type polysilicon to form gates and electrodes in semiconductor devices (col. 4, ll. 15-20; col. 4, ll. 1-5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the gate electrode, floating electrode, and field plate electrode of Gao and Kondo containing N-type polysilicon for the purpose of utilizing an art recognized material known to be suitable for use gates and electrodes (as exemplified by Matsuoka at col. 4, ll. 15-20).
Regarding claim 8, Gao and Kondo disclose the semiconductor device according to claim 1, however fail to expressly disclose: wherein the gate electrode, the floating electrode, and the field plate electrode contain P-type polysilicon or a metal material.
In the same field of endeavor, Matsuoka discloses the use of P-type polysilicon to form gates and electrodes in semiconductor devices (col. 4, ll. 15-20; col. 4, ll. 1-5 and col. 12, ll. 1-3 - disclosing N-type or P-type). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the gate electrode, floating electrode, and field plate electrode of Gao and Kondo containing P-type polysilicon for the purpose of utilizing an art recognized material known to be suitable for use gates and electrodes (as exemplified by Matsuoka at col. 4, ll. 15-20).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Gao and Kondo as applied to claim 1 above, and further in view of US 2013/0134505 A1 to Kobayashi (hereinafter “Kobayashi”).
Regarding claim 5, Gao and Kondo disclose the semiconductor device according to claim 1, however fail to expressly disclose: wherein the insulating film contains silicon nitride.
In the same field of endeavor, Kobayashi discloses the use of silicon nitride to form insulating films in semiconductor devices (¶ 0016). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide silicon nitride as the insulating film of Gao and Kondo for the purpose of utilizing an art recognized material known to be suitable for use in insulating films (as exemplified by Kobayashi at ¶ 0016).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CANDICE Y. CHAN
Examiner
Art Unit 2813
27 March 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813