CTNF 18/515,259 CTNF 81650 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-4, 6-8, 11-14, and 19 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Werber et al. (US 2015/0014743) (“Werber”) . With regard to claim 1, fig. 4A of Werber discloses a method for manufacturing a semiconductor apparatus including: a transistor 410a portion provided in a semiconductor substrate 100 of a first conductivity type (n) and including a base region 115 of a second conductivity type (p); a diode portion 410b provided in the semiconductor substrate 100 and including an anode region 116 of the second conductivity type (p); and a first trench contact (302 in 410b) provided in the diode portion 410b on a front surface side 101 of the semiconductor substrate 100, the method comprising: acquiring a condition of trade-off between a reverse recovery loss (“reverse recovery losses”, par p0046]) of the diode portion 410b and a forward voltage (“forward voltage”, par [0042]) of the diode portion 410b; deciding a target characteristic required for the semiconductor apparatus 600; determining whether a first depth 332 of the first trench contact 332 according to the target characteristic (“reduce switching losses”, par [0001]) satisfies a diode condition which is a condition (“reduce switching losses”, par [0001]) for realizing the target characteristic (“reduce switching losses”, par [0001]), of the condition of trade-off; and manufacturing the semiconductor apparatus 600 in which a depth 332 of the first trench contact (302 in 410b) is the first depth 332. With regard to claim 2, fig. 4A of Werber discloses that the determining whether the first depth 332 satisfies the diode condition (“reduce switching losses”, par [0001]) includes: acquiring the diode condition for a case where a doping concentration (“impurity concentration”, par [0056]) of the anode region 116 is a first doping concentration (“impurity concentration”, par [0056]); and determining whether the first depth 332 satisfies the diode condition at the first doping concentration (“impurity concentration”, par [0056]). With regard to claim 3, fig. 4A of Werber discloses that the first doping concentration (“impurity concentration”, par [0056]) is a doping concentration (“impurity concentration”, par [0048]) of the base region 115. With regard to claim 4, fig. 4A of Werber discloses that if the first depth 332 satisfies the diode condition (“reduce switching losses”, par [0001]) at the first doping concentration (“impurity concentration”, par [0056]), the manufacturing the semiconductor apparatus 600 includes manufacturing the semiconductor apparatus 600 in which the depth 332 of the first trench contact is the first depth 332, and if the first depth 332 does not satisfy the diode condition at the first doping concentration (“impurity concentration”, par [0056]), the determining whether the first depth 332 satisfies the diode condition (“reduce switching losses”, par [0001]) includes: acquiring the diode condition (“reduce switching losses”, par [0001]) for a case where the doping concentration (“decreasing impurity concentration”, par [0056]) of the anode region 116 is a second doping concentration lower (“decreasing impurity concentration”, par [0056]) than the first doping concentration (“impurity concentration”, par [0056]); and determining whether the first depth 332 satisfies the diode condition (“reduce switching losses”, par [0001]) at the second doping concentration (“decreasing impurity concentration”, par [0056]). With regard to claim 6, fig. 4A of Werber discloses that the semiconductor apparatus 600 includes a second trench contact (302 in 410a) provided in the transistor portion 410a on the front surface side 101 of the semiconductor substrate 100, the method comprising: acquiring a threshold condition indicating a relationship between a depth (“ trench contacts 302 reach the body zones 115 at a distance to the first surface 101”, par [0062]) of the second trench contact (302 in 410a) and a threshold voltage of the transistor portion 410a; and determining whether a second depth (“ trench contacts 302 reach the body zones 115 at a distance to the first surface 101”, par [0062]) of the second trench contact (302 in 410a) according to the target characteristic satisfies a transistor condition which is a condition for realizing the target characteristic, of the threshold condition, and the manufacturing the semiconductor apparatus 600 includes manufacturing the semiconductor apparatus 600 in which the depth of the second trench contact (302 in 410a) is the second depth (“ trench contacts 302 reach the body zones 115 at a distance to the first surface 101”, par [0062]). With regard to claim 7, fig. 4A of Werber discloses that the determining whether the first depth 332 satisfies the diode condition includes: acquiring the diode condition for a case where a doping concentration of the anode region 116 is a doping concentration of the base region 115; and determining whether the first depth 332 satisfies the diode condition at the doping concentration of the base region 115. With regard to claim 8, fig. 4A of Werber discloses that the determining whether the second depth (“trench contacts 302 reach the body zones 115 at a distance to the first surface 101”, par [0062]) satisfies the transistor condition includes determining whether the second depth (“ trench contacts 302 reach the body zones 115 at a distance to the first surface 101”, par [0062]), which is a same as the first depth 332, satisfies the transistor condition. With regard to claim 11, fig. 4A of Werber discloses that the diode condition includes a condition according to the depth 332 of the first trench contact (302 in 410b) within a predetermined range 332, the determining whether the first depth 332 satisfies the diode condition includes determining whether the first depth 332 is included in the predetermined range 332. With regard to claim 12, fig. 4A of Werber discloses that the diode condition includes a condition according to the depth 332 of the first trench contact (302 in 410b) within a predetermined range 332, the determining whether the first depth 332 satisfies the diode condition includes determining whether the first depth 332 is included in the predetermined range 332. With regard to claim 13, fig. 4A of Werber discloses that the diode condition includes a condition according to the depth 332 of the first trench contact (302 in 410b) within a predetermined range 332, the determining whether the first depth 332 satisfies the diode condition includes determining whether the first depth 332 is included in the predetermined range 332. With regard to claim 14, fig. 4A of Werber discloses that the diode condition includes a condition according to the depth 332 of the first trench contact (302 in 410b) within a predetermined range 332, the determining whether the first depth 332 satisfies the diode condition includes determining whether the first depth 332 is included in the predetermined range 332. With regard to claim 19, fig. 4A of Werber discloses that the semiconductor apparatus 600 includes an emitter region 110 of the first conductivity type (n) provided above the base region 115, and the second depth (“ trench contacts 302 reach the body zones 115 at a distance to the first surface 101”, par [0062]) is deeper than a depth from the front surface 101 of the semiconductor substrate 100 to a lower end (bottom of 110) of the emitter region 110 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Werber et al. (US 2015/0014743) (“Werber”) in view of Guan et al. (US 2017/0110404) (“Guan”) . With regard to claim 15, Werber does not disclose that the first depth is 0 μm or more and 1.0 μm or less. However, fig. 1C of Guan discloses the first depth is 0 μm or more (“0.3 um”, par [0034]) and 1.0 μm or less. Therefore, it would have been obvious to one of ordinary skill in the art to form the contact trench of Werber with the depth of Guan in order to provide a suitable depth that will not cause a negative effect on breakdown voltage of the diode. See par [0034] of Guan. With regard to claim 16, Werber does not disclose that the first depth is 0.3 μm or more and 0.4 μm or less. However, fig. 1C of Guan discloses that the first depth is 0.3 μm (“0.3 um”, par [0034]) or more and 0.4 μm or less. Therefore, it would have been obvious to one of ordinary skill in the art to form the contact trench of Werber with the depth of Guan in order to provide a suitable depth that will not cause a negative effect on breakdown voltage of the diode. See par [0034] of Guan . 07-21-aia AIA Claim s 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Werber et al. (US 2015/0014743) (“Werber”) in view of Sandow et al. (US 2021/0296474) (“Sandow”) . With regard to claim 18, Werber does not disclose the semiconductor apparatus includes a plug contact region of the second conductivity type provided below the first trench contact and having a higher doping concentration than the base region. However, fig. 2A of Sandow discloses that the semiconductor apparatus includes a plug contact region 148 of the second conductivity type (“highly doped region 148 of the second conductivity type”, par [0028]) provided below the first trench contact 146 and having a higher doping concentration (“highly doped region 148”, par [0024]) than the base region 122. Therefore, it would have been obvious to one of ordinary skill in the art to form the trench contact of Werber with the high doped region underneath as taught in Sandow in order to provide for good ohmic contact with the metallization. See par [0030] of Sandow. With regard to claim 20, the semiconductor apparatus includes a plug contact region of the second conductivity type provided below the first trench contact and the second trench contact and having a higher doping concentration than the base region. However, figs. 2A-2B of Sandow discloses that the semiconductor apparatus includes a plug contact region 148 of the second conductivity type (“highly doped region 148 of the second conductivity type”, par [0028]) provided below the first trench contact 146 and the second trench contact 144 and having a higher doping concentration (“highly doped region 148”, par [0024]) than the base region 122. Therefore, it would have been obvious to one of ordinary skill in the art to form the trench contact of Werber with the high doped region underneath as taught in Sandow in order to provide for good ohmic contact with the metallization. See par [0030] of Sandow . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 5, 9-10, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at 571 270-3035. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BENJAMIN TZU-HUNG LIU/ Primary Examiner, Art Unit 2893 Application/Control Number: 18/515,259 Page 2 Art Unit: 2893 Application/Control Number: 18/515,259 Page 3 Art Unit: 2893 Application/Control Number: 18/515,259 Page 4 Art Unit: 2893 Application/Control Number: 18/515,259 Page 5 Art Unit: 2893 Application/Control Number: 18/515,259 Page 6 Art Unit: 2893 Application/Control Number: 18/515,259 Page 7 Art Unit: 2893 Application/Control Number: 18/515,259 Page 8 Art Unit: 2893 Application/Control Number: 18/515,259 Page 9 Art Unit: 2893 Application/Control Number: 18/515,259 Page 10 Art Unit: 2893