Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under AIA 35 U.S.C. 103 as being unpatentable over US 6,218,256 to Agarwal in view of US 2022/0310779 to Kuo.
As per claim 1, Agarwal discloses a method of manufacturing a capacitor, comprising:
forming a bottom electrode layer (see first electrode 12 in Fig 3); forming an insulator (see dielectric 14 in fig 4) on the bottom electrode layer; crystallizing the insulator (see Col 7 line 66-67); and forming a top electrode layer (see second electrode 18 in Fig 6) on the crystallized insulator (see Fig 2-6 and 8-9; see Col 4 line 27 – Col 7 line 8 and Col 7 line 32 – Col 10 line 8).
As per claim 1, Agarwal discloses the elements of the current invention as detailed above with respect to claim 1. Agarwal further discloses that the insulator can include metal oxides (see Col 4 line 55-57), but does not explicitly disclose that the insulator is a composite layer with aluminum hydroxide sandwiched by two zirconium dioxide layers. However, the use of composite insulators made of multiple layers including aluminum hydroxide and/or zirconium dioxide are well-known in the art.
Kuo discloses a similar capacitor and method of manufacturing the capacitor (see Fig and 4 and step 58 of Fig 5), wherein an insulator (see high-k dielectric layers 24 in Fig 2 and 4) of the capacitor can be ZAZ laminate comprising layers of ZrO2 and Al2O3 arranged in the order ZrO2—Al2O3—ZrO2 (see Fig 2; see Para 0011, 0016, 0019, and 0033) which is known in the art for having a high dielectric constant k which increases the ability of the capacitor to store charge.
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the insulator of Agarwal with the high-k dielectric layer of Kuo that includes a composite layer with aluminum hydroxide sandwiched by two zirconium dioxide layers. One of ordinary skill in the art would recognize that it has been held that a selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill and a mere change in the composition and/or proportion of constituents of a layer is nothing more than one of numerous compositions and proportions that one of ordinary skill in the art would find obvious to provide based on the suitability for the intended final application, that ZrO2 and Al2O3 are both well-known insulating materials used alone or in combination for capacitors, and further that the inventios of Agarwal and Kuo are both directed towards methods of manufacturing capacitors and therefore it would have been a routine matter for one of ordinary skill in the art to look to Luo for improvements for Agarwal; the obvious advantages of using a ZrO2—Al2O3—ZrO2 laminate as the insulator for the capacitor as taught by Kuo (Kuo: Para 0011, 0016, 0019, and 0033) is that these laminates are known in the art for their high dielectric constant k which would increase the ability of the capacitor to store charge as would be generally understood by one of ordinary skill in the art.
As per claim 2, Agarwal and Kuo disclose the elements of the current invention as detailed above with respect to claim 1. Agarwal further discloses that the step of crystallizing the insulator is performed through an anneal treatment (see Col 7 line 66-67).
As per claim 3, Agarwal and Kuo disclose the elements of the current invention as detailed above with respect to claim 1. Agarwal further discloses that the step of crystallizing the insulator is performed before the step of forming the top electrode layer (see Col 7 line 32 – Col 10 line 8 that discloses that the dielectric is annealed/crystallized after it is deposited before the second electrode 18 is deposited).
As per claim 4, Agarwal and Kuo disclose the elements of the current invention as detailed above with respect to claim 1, Agarwal further discloses forming an oxide diffusion barrier layer (see barrier layer 16 in Fig 5-6A and/or barrier layers 16A and 16B in Fig 6B; see Col 5 line 27-63 and Col 8 line 33 – Col 9 line 25 that discuss the composition of the barrier layers 16,16A,16B that can include TiN that is oxygen annealed to be oxygen rich with oxygen bonding open bonding sites) between the insulator and the top electrode layer (see Fig 6A and 6B).
Claims 5, 7-8, and 10-14 are rejected under AIA 35 U.S.C. 103 as being unpatentable over US 6,218,256 to Agarwal and US 2022/0310779 to Kuo in further view of US 2003/0008456 to Kim.
As per claim 5, Agarwal and Kuo disclose the elements of the current invention as detailed above with respect to claim 4. Agarwal further discloses that the oxide diffusion barrier layer can comprise titanium nitride this is oxygen annealed to be oxygen rich (see Col 5 line 27-63 and Col 8 line 33-60 that disclose that the barrier layers 16,16A,16B can be TiN that is oxygen annealed to be oxygen rich), which presumably would result in titanium oxynitride, but Agarwal does not explicitly disclose that the oxide diffusion barrier layer is titanium oxynitride.
Kim discloses a similar method of manufacturing a capacitor including forming a bottom electrode layer (see lower electrode 110 in Fig 1), forming an insulator (see dielectric layer 115 in Fig 2) on the bottom electrode layer, crystallizing the insulator (see Para 0028 line 7-14), forming a top electrode layer (see second TiN layer 130 in Fig 6) on the crystallized insulator, and forming an oxide diffusion barrier layer (see first TiN layer that is oxidized to form TiON layer in Fig 6) between the insulator and the top electrode, wherein the oxide diffusion barrier layer comprises titanium oxynitride (see Para 0029-0031).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the oxygen rich TiN barrier layer of Agarwal to explicitly be titanium oxynitride as taught by Kim. One of ordinary skill in the art would recognize that it has been held that a selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill and a mere change in the composition and/or proportion of constituents of a layer is nothing more than one of numerous compositions and proportions that one of ordinary skill in the art would find obvious to provide based on the suitability for the intended final application, and further that the inventios of Agarwal and Kim are both directed towards methods of manufacturing capacitors with oxide diffusion barrier layers comprising elements titanium, oxygen, and nitrogen and therefore it would have been a routine matter for one of ordinary skill in the art to look to Kim for improvements for Agarwal; the obvious advantages of using titanium oxynitride for the oxide diffusion barrier layer being that this would allow prevent the insulator layer from deteriorating by suppressing the leakage current generated by deoxidizing the insulator materials (Kim: Para 0034).
As per claims 7-8, Agarwal and Kuo disclose the elements of the current invention as detailed above with respect to claim 1. Agarwal is silent regarding the crystallizing process of the insulator and therefore does not disclose that a temperature of the step of crystallizing the insulator is in a range from 400 degrees to 600 degrees or has a time period in a range from 30 seconds to 100 seconds.
Kim discloses a similar method of manufacturing a capacitor including forming a bottom electrode layer (see lower electrode 110 in Fig 1), forming an insulator (see dielectric layer 115 in Fig 2) on the bottom electrode layer, crystallizing the insulator (see Para 0028 line 7-14), and forming a top electrode layer (see second TiN layer 130 in Fig 6) on the crystallized insulator, wherein the step of crystallizing the insulator includes a temperature of in a range from 400 degrees to 600 degrees (500-650°C) applied for a time period in a range from 30 seconds to 100 seconds (30-60 seconds) (see Para 0028 line 7-14).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the crystallization step of the insulator of Agarwal to include a temperature between 500-600 degrees Celsius for a time period of 30-60 seconds as taught by Kim. One of ordinary skill in the art would recognize that it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges of process temperatures and/or processing times would involve only ordinary skill in the art, and therefore it would have been an obvious design choice for one of ordinary skill in the art to choose the above temperature ranges and/or process times for the crystallization step of the insulator as taught by Kim and further that the inventios of Agarwal and Kim are both directed towards methods of manufacturing capacitors including crystallizing the insulator and therefore it would have been a routine matter for one of ordinary skill in the art to look to Kim for improvements for Agarwal; the obvious advantages crystallizing the insulator at a temperature between 500-600 degrees for a time period of 30-60 seconds being that this would effectively stabilize the interface of the insulator and the bottom electrode and increasing the inductive capacity of the insulator (Kim: Para 0028 line 7-14).
As per claim 10, Agarwal discloses a method of manufacturing a capacitor, comprising:
forming a bottom electrode layer (see first electrode 12 in Fig 3); forming an insulator (see dielectric 14 in fig 4) on the bottom electrode layer; forming a oxidized titanium nitride layer (see Col 5 line 27-63 and Col 8 line 33-60 that disclose that the barrier layers 16,16A,16B can be TiN that is oxygen annealed to be oxygen rich) on the insulator; and forming a top electrode layer (see second electrode 18 in Fig 6) on the crystallized insulator (see Fig 2-6 and 8-9; see Col 4 line 27 – Col 7 line 8 and Col 7 line 32 – Col 10 line 8).
As per claim 10, Agarwal discloses the elements of the current invention as detailed above with respect to claim 10. Agarwal further discloses that the insulator can include metal oxides (see Col 4 line 55-57), but does not explicitly disclose that the insulator is a composite layer with aluminum hydroxide sandwiched by two zirconium dioxide layers. However, the use of composite insulators made of multiple layers including aluminum hydroxide and/or zirconium dioxide are well-known in the art.
Kuo discloses a similar capacitor and method of manufacturing the capacitor (see Fig and 4 and step 58 of Fig 5), wherein an insulator (see high-k dielectric layers 24 in Fig 2 and 4) of the capacitor can be ZAZ laminate comprising layers of ZrO2 and Al2O3 arranged in the order ZrO2—Al2O3—ZrO2 (see Fig 2; see Para 0011, 0016, 0019, and 0033) which is known in the art for having a high dielectric constant k which increases the ability of the capacitor to store charge.
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the insulator of Agarwal with the high-k dielectric layer of Kuo that includes a composite layer with aluminum hydroxide sandwiched by two zirconium dioxide layers. One of ordinary skill in the art would recognize that it has been held that a selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill and a mere change in the composition and/or proportion of constituents of a layer is nothing more than one of numerous compositions and proportions that one of ordinary skill in the art would find obvious to provide based on the suitability for the intended final application, that ZrO2 and Al2O3 are both well-known insulating materials used alone or in combination for capacitors, and further that the inventios of Agarwal and Kuo are both directed towards methods of manufacturing capacitors and therefore it would have been a routine matter for one of ordinary skill in the art to look to Luo for improvements for Agarwal; the obvious advantages of using a ZrO2—Al2O3—ZrO2 laminate as the insulator for the capacitor as taught by Kuo (Kuo: Para 0011, 0016, 0019, and 0033) is that these laminates are known in the art for their high dielectric constant k which would increase the ability of the capacitor to store charge as would be generally understood by one of ordinary skill in the art.
As per claim 10, Agarwal and Kuo disclose the elements of the current invention as detailed above with respect to claim 10. While Agarwal discloses that the oxide diffusion barrier layer can comprise titanium nitride this is oxygen annealed to be oxygen rich (see Col 5 line 27-63 and Col 8 line 33-60 that disclose that the barrier layers 16,16A,16B can be TiN that is oxygen annealed to be oxygen rich), which presumably would result in titanium oxynitride, Agarwal does not explicitly disclose that the oxide diffusion barrier layer is titanium oxynitride.
Kim discloses a similar method of manufacturing a capacitor including forming a bottom electrode layer (see lower electrode 110 in Fig 1), forming an insulator (see dielectric layer 115 in Fig 2) on the bottom electrode layer, crystallizing the insulator (see Para 0028 line 7-14), forming a top electrode layer (see second TiN layer 130 in Fig 6) on the crystallized insulator, and forming an oxide diffusion barrier layer (see first TiN layer that is oxidized to form TiON layer in Fig 6) between the insulator and the top electrode, wherein the oxide diffusion barrier layer comprises titanium oxynitride (see Para 0029-0031).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the oxygen rich TiN barrier layer of Agarwal to explicitly be titanium oxynitride as taught by Kim. One of ordinary skill in the art would recognize that it has been held that a selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill and a mere change in the composition and/or proportion of constituents of a layer is nothing more than one of numerous compositions and proportions that one of ordinary skill in the art would find obvious to provide based on the suitability for the intended final application, and further that the inventios of Agarwal and Kim are both directed towards methods of manufacturing capacitors with oxide diffusion barrier layers comprising elements titanium, oxygen, and nitrogen and therefore it would have been a routine matter for one of ordinary skill in the art to look to Kim for improvements for Agarwal; the obvious advantages of using titanium oxynitride for the oxide diffusion barrier layer being that this would allow prevent the insulator layer from deteriorating by suppressing the leakage current generated by deoxidizing the insulator materials (Kim: Para 0034).
As per claim 11, Agarwal, Kuo, and Kim disclose the elements of the current invention as detailed above with respect to claim 10. Agarwal further discloses performing an anneal treatment to the insulator (see Col 7 line 66-67).
As per claim 12, Agarwal, Kuo, and Kim disclose the elements of the current invention as detailed above with respect to claim 11. Agarwal further discloses that the anneal treatment is performed before forming the top electrode layer (see Col 7 line 32 – Col 10 line 8 that discloses that the dielectric is annealed/crystallized after it is deposited before the second electrode 18 is deposited).
As per claim 13, Agarwal, Kuo, and Kim disclose the elements of the current invention as detailed above with respect to claim 11. Kim further discloses that a temperature of the step of performing the anneal treatment is in a range from 400 degrees to 600 degrees (500-650°C; see Para 0028 line 7-14).
As per claim 14, Agarwal, Kuo, and Kim disclose the elements of the current invention as detailed above with respect to claim 11. Kim further discloses that a time period of the step of performing the anneal treatment is in a range from 30 seconds to 100 seconds (30-60 seconds; see Para 0028 line 7-14).
Claim 6 is rejected under AIA 35 U.S.C. 103 as being unpatentable over US 6,218,256 to Agarwal and US 2022/0310779 to Kuo in further view of US 2006/0273366 to Ko.
As per claim 6, Agarwal and Kuo disclose the elements of the current invention as detailed above with respect to claim 1. Agarwal further discloses that the bottom electrode layer can include titanium nitride (see Col 4 liner 3-4) or a deposited metal layer of titanium, tungsten, chromium, platinum, ruthenium or iridium, or ruthenium-oxide or iridium-oxide or combinations thereof with or without silicon (see Col 4 line 43-50), which could presumably result in titanium silicon nitride, but Agarwal does not explicitly disclose that the bottom electrode layer is titanium silicon nitride. However, It has been held that a selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill and a mere change in the composition of a material layer is nothing more than one of numerous compositions that one of ordinary skill in the art would find obvious to provide based on the suitability for the intended final application.
Ko discloses a similar method of manufacturing a capacitor including forming a bottom electrode layer (see lower electrode layer 130 including first lower electrode film 120 and a second lower electrode film 125 in Fig 4B), forming an insulator (see ferroelectric layer 135 in Fig 4C) on the bottom electrode layer, and forming a top electrode layer (see upper electrode layer 140 in Fig 4C) on the insulator, wherein the bottom electrode layer can be made of titanium silicon nitride (see Para 0075).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the titanium nitride and/or titanium with silicone bottom electrode layer material to be made of titanium silicon nitride as taught by Ko. One of ordinary skill in the art would recognize that it has been held that a selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill and a mere change in the composition and/or proportion of constituents of a layer is nothing more than one of numerous compositions and proportions that one of ordinary skill in the art would find obvious to provide based on the suitability for the intended final application, and further that the inventios of Agarwal and Kim are both directed towards methods of manufacturing capacitors with electrodes comprising elements titanium, silicon, and nitrogen and therefore it would have been a routine matter for one of ordinary skill in the art to look to Ko for improvements for Agarwal; the obvious advantages of using titanium silicon nitride being that titanium silicon nitride is a known material for electrodes of a capacitor known in the art and therefore would provide electrical and structural properties necessary for a capacitor as would be generally understood by one of ordinary skill in the art.
Claim 9 is rejected under AIA 35 U.S.C. 103 as being unpatentable over US 6,218,256 to Agarwal and US 2022/0310779 to Kuo in further view of JP 2011-199071 to Fujitsu (translation previously provided by examiner).
As per claim 9, Agarwal and Kuo disclose the elements of the current invention as detailed above with respect to claim 1. Agarwal discloses that the time period of the step of crystallizing the insulator is in a range from 30 seconds to 60 seconds (see Para 0028 line 7-14), but is silent regarding the time period for forming the top electrode layer. However, it is well within the skill of one of ordinary skill in the art to determine an appropriate amount of time for forming process of an electrode and/or a crystallization process, for example to form the electrode to a desired thickness, or provide a desired crystallinity, etc.; therefore it would have been an obvious choice to one of ordinary skill in the art to make a time period of the step of forming the top electrode layer longer then a crystallization step of the insulator with the reasonable expectation that this would allow for the top electrode to have a greater thickness with greater structural integrity. Further, Fujitsu discloses a method of making a capacitor, wherein a step of forming a single electrode film (see electrode film 72 in Fig 26) of a three layer upper electrode (see upper electrode 76 in Fig 26) takes a time period of 79 seconds (see translation Page 28) which is longer than the 30-60 second time period of the crystallization step of Agarwal.
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the time period of forming the top electrode layer of Agarwal to be longer than the step of crystallizing the insulator as taught by Fujitsu. One of ordinary skill in the art would recognize that it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges of the time periods for manufacturing processes involves only ordinary skill in the art, and therefore it would have been an obvious design choice for one of ordinary skill in the art to determine appropriate time periods for manufacturing steps such as crystallization and deposition of electrode layers, and further that the inventios of Agarwal and Fujitsu are both directed towards methods of manufacturing capacitors and therefore it would have been a routine matter for one of ordinary skill in the art to look to Fujitsu for improvements for Agarwal; the obvious advantages of taking a longer period of time for the formation of the top electrode being that this would allow for multiple upper electrode layers to be formed as taught by Fujitsu that would allow for greater customization of the material properties of the top electrode layer as would be generally understood by one of ordinary skill in the art.
Response to Arguments
Applicant’s arguments, see Applicant’s response, filed 11/18/2025, with respect to the rejection(s) of claim(s) 1 under AIA 35 U.S.C. 102(a)(1) as being anticipated by US 6,218,256 to Agarwal and claim(s) 10 under AIA 35 U.S.C. 103 as being unpatentable over US 6,218,256 to Agarwal in view of US 2003/0008456 to Kim have been fully considered and are persuasive in light of the claim amendments filed 11/18/2025. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 2022/0310779 to Kuo (see above 103 rejections for more details).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joshua D. Anderson, whose telephone number is (571) 270-0157. The examiner can normally be reached from Monday to Friday between 7 AM and 1 PM Arizona time.
If any attempt to reach the examiner by telephone is unsuccessful, the examiner’s supervisor, Thomas Hong, can be reached at (571) 272-0993.
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/JOSHUA D ANDERSON/
Examiner, Art Unit 3729
/THOMAS J HONG/Supervisory Patent Examiner, Art Unit 3729