DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant' s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Based on the previously cited prior arts Nagaya, Nomoto, and Rieske and new references Bayless (US20190148335A1) and Nakajima (US20150380291A1) the claims 1-3, 5-10 are rejected.
Response to Amendment
Applicant’s amendments to claims 1 and 5 has been fully considered. Applicant’s cancellation of claim 4 has been acknowledged. Applicant’s newly added claims 8 – 10 have been fully considered and examined.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites “forming a first deformation restriction layer and a second deformation restriction layer on a first main surface and a second main surface of a semiconductor substrate”; this should be written as “forming a first deformation restriction layer and a second deformation restriction layer on a first main surface and a second main surface of a semiconductor substrate respectively.”
Appropriate correction is required.
Specification
The disclosure is objected to because of the following informalities:
[0029] recites “both end portions of the light focusing plate 3 of the semiconductor substrate 1”; this should be written as “both end portions of the light focusing plane 3 of the semiconductor substrate 1.”
[0035] recites “first main surface 10a and a second main surface 10b”; this should be written as “first main surface 1a and a second main surface 1b” to be consistent with the rest of the disclosure and the figures.
[0038] recites “the second deformation restriction layer 40 may be formed so as to cover the covered end surface 1d”; this should be written as “the second deformation restriction layer 40 may be formed so as to cover the curved end surface 1d.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, and 7 - 10 are rejected under 35 U.S.C. 103 as being unpatentable over Nagaya et al. (US20210327757A1; hereinafter Nagaya) in view of Bayless et al. (US20190148335A1; hereinafter Bayless), further in view of Nakajima (US20150380291A1; hereinafter Nakajima).
Regarding Claim 1 (Amended), Nagaya discloses a manufacturing method of a semiconductor device (manufacturing process of the semiconductor chip 100), FIGS. 1A-1J, [0033], comprising:
forming a first deformation restriction layer (holding member 20, FIG. 1D, [0037]) and a second deformation restriction layer (auxiliary member 50, FIG. 1G, [0051]) on a first main surface (10a) and a second main surface (10b) of a semiconductor substrate (processed wafer 10), the first main surface (10a) being opposite to the second main surface (10b), and the semiconductor substrate (10) having a device structure (element component 11) formed adjacent to the first main surface (10a), FIG. 1C, [0035], [0036].
applying a laser beam (laser beam L) through the second main surface (10b) of the semiconductor substrate (10) so as to irradiate a plane extending at a predetermined depth (wafer transformation layer 15 extending along the surface direction at the predetermined depth L) inside of the semiconductor substrate (10) with the laser beam (L), FIG. 1F reproduced below, [0043]; and
peeling off a device layer (wafer is divided into the chip formation wafer 30 and the recycle wafer 40 at the wafer transformation layer 15) that is a part of the semiconductor substrate (10) including the first main surface (10a) and the device structure (11) from a remaining layer (40) of the semiconductor substrate along the plane irradiated with the laser beam (along the plane defined by the wafer transformation layer 15), FIG. 1G reproduced below, [0051].
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Nagaya: FIGS. 1F, 1G
Nagaya does not disclose “applying a laser beam through the second deformation restriction layer on the second main surface of the semiconductor substrate; wherein the semiconductor substrate has a curved end surface having a curved shape at a peripheral end of the second main surface, in the forming of the first deformation restriction layer and the second deformation restriction layer, the second deformation restriction layer is formed so as to cover the curved end surface, a surface of the second deformation restriction layer opposite to the semiconductor substrate in a thickness direction of the semiconductor substrate is a flat surface including a region overlapping the curved end surface, and in the applying of the laser beam, the laser beam is applied in a direction orthogonal to the flat surface of the second deformation restriction layer including the region.”
In a similar art, Bayless discloses methods and systems for processing semiconductor device structures [0002].
Bayless [0024] discloses a semiconductor structure 108 including an active surface 110 and an inactive surface 112. Bayless [0027] discloses the carrier structure 100 may be temporarily secured to the semiconductor device structure 108 with first adhesive material 102 and second adhesive material 116, and barrier material 106. Bayless [0037] discloses the laser beam 132 passes through 100 and first adhesive material 102 to release its temporary attachment to the carrier structure 108.
Bayless [0045] discloses that those of ordinary skill in the art will understand that the methods and system of the disclosure may be employed with a semiconductor device structure 108 may be adhered with the active surface facing away from the carrier structure 100. Therefore, the carrier structure 100 along with adhesive material 102 corresponds to the claimed second deformation restriction layer when arranged with the active surface facing away from the carrier structure 100.
Bayless discloses: applying a laser beam (132) through the second deformation restriction layer (structure including carrier structure 100 and first adhesive material 102) on the second main surface (inactive surface 112) of the semiconductor substrate (108), FIG. 9, [0024], [0027], [0037], [0045].
Bayless discloses that a method as taught reduces stress on the semiconductor substrate and increases yield [0002]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nagaya’s method in order to reduce stress and increase yield as disclosed by Bayless [0002].
In a similar art, Nakajima discloses a method for manufacturing a semiconductor device [0048].
Nakajima discloses: wherein the semiconductor substrate (wafer 1) has a curved end surface having a curved shape at a peripheral end of the second main surface (chamfered portion 1b with R-plane curvature), FIG. 4, [0049].
Nakajima FIG. 5, [0052] discloses a glass substrate 3 is bonded to wafer 1 through adhesive layer 2 and glass substrate 3 reinforces wafer 1. Nakajima [0060] discloses laser beam 13 is radiated through glass substrate 3. The glass substrate 3 and adhesive layer 2 together correspond to the claimed second deformation restriction. In addition, Bayless [0045] discloses that the semiconductor wafer may be adhered with the active surface facing towards or away from the carrier.
The combination of Nagaya, Bayless, and Nakajima discloses: in the forming of the first deformation restriction layer (Nagaya: 20) and the second deformation restriction layer (Nakajima: structure including substrate 3 and adhesive layer 2), the second deformation restriction layer (Nakajima: structure including substrate 3 and adhesive layer 2) is formed so as to cover the curved end surface (Nakajima: 1b, FIG. 5, [0059]).
a surface (Nakajima: surface 3d) of the second deformation restriction layer (Nakajima: structure including substrate 3 and layer 2) opposite to the semiconductor substrate (Nakajima: wafer 1) in a thickness direction of the semiconductor substrate (Nakajima: vertical direction of wafer 1) is a flat surface including a region overlapping the curved end surface (Nakajima: structure including 3 and 2 has the top flat surface 3d and the peripheral region of the structure including 3 and 2 overlapping the curved end surface 1b), FIG. 5, [0059], [0067].
in the applying of the laser beam (Nakajima: 13), the laser beam is applied in a direction orthogonal to the flat surface (Nakajima: 3d, FIG. 5, [0062]) of the second deformation restriction layer including the region (Nakajima: structure including 3 and 2 has the top flat surface 3d and the peripheral region of the structure including 3 and 2 overlapping the curved end surface 1b), FIG. 5, [0059], [0067].
Nakajima discloses that a method as taught prevents stress at the wafer peripheral ends and prevents chipping, cracking or breaking of the wafer [0063]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nagaya and Bayless’ method in order to prevent stress at the wafer peripheral ends and prevents chipping, cracking or breaking as disclosed by Nakajima [0063].
Regarding Claim 2, The combination of Nagaya, Bayless, and Nakajima discloses the manufacturing method according to claim 1.
Nagaya discloses: wherein at least one of the first deformation restriction layer (20) and the second deformation restriction layer (50) includes an organic layer made of an organic material (20 and 50 include an adhesive made of ultraviolet curable resin which is an organic layer), [0051].
Regarding Claim 5 (Amended), The combination of Nagaya, Bayless, and Nakajima discloses the manufacturing method according to claim 1.
Nagaya discloses: wherein in the forming of the first deformation restriction layer (20) and the second deformation restriction layer (50), FIGS. 1D, 1G, [0037], [0051],
Bayless discloses: the second deformation restriction layer (structure including carrier structure 100 and first adhesive material 102) is formed so as not to cover a portion of a side surface of the semiconductor substrate (a portion of the side surface of 108 is not covered as shown in FIG. 4), [0027].
The combination of Nagaya, Bayless, and Nakajima discloses: a portion of the side surface of the semiconductor substrate (Bayless: a portion of the side surface of 108) corresponding to the plane, extending at the predetermined depth and irradiated with the laser beam (Nagaya: the plane defined by the wafer transformation layer 15 at a predetermined depth L irradiated with laser beam L, FIG. 1F, [0043]).
Bayless discloses that a method as taught reduces stress on the semiconductor substrate and increases yield [0002]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to reduce stress and increase yield as disclosed by Bayless [0002].
Regarding Claim 7, The combination of Nagaya, Bayless, and Nakajima discloses the manufacturing method according to claim 1.
Nagaya discloses: wherein the semiconductor substrate (10) is a nitride semiconductor substrate (processed wafer 10 includes Gallium Nitride wafer 1, [0034]).
Regarding Claim 8, (New) The combination of Nagaya, Bayless, and Nakajima discloses the manufacturing method according to claim 1.
Nagaya discloses: wherein in the forming of the first deformation restriction layer (20) and the second deformation restriction layer (50), FIG. 1G, [0037], [0051].
Nagaya does not disclose “the second deformation restriction layer is formed to extend laterally beyond a side surface of the semiconductor substrate thereby to cover the curved end surface.”
Nakajima discloses: the second deformation restriction layer (structure including glass substrate 3 and adhesive layer 2) is formed to extend laterally beyond a side surface (1a) of the semiconductor substrate (wafer 1) thereby to cover the curved end surface (1b), FIG. 5, [0049], [0059].
Nakajima discloses that a method as taught prevents stress at the wafer peripheral ends and prevents chipping, cracking or breaking of the wafer [0063]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to prevent stress at the wafer peripheral ends and prevents chipping, cracking or breaking as disclosed by Nakajima [0063].
Regarding Claim 9, (New) The combination of Nagaya, Bayless, and Nakajima discloses the manufacturing method according to claim 1.
Nagaya does not disclose “wherein the second deformation restriction layer extends over an entirety of the curved end surface.”
Nakajima discloses: wherein the second deformation restriction layer (structure including glass substrate 3 and adhesive layer 2) extends over an entirety of the curved end surface (1b), FIG. 5, [0049], [0059].
Nakajima discloses that a method as taught prevents stress at the wafer peripheral ends and prevents chipping, cracking or breaking of the wafer [0063]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to prevent stress at the wafer peripheral ends and prevents chipping, cracking or breaking as disclosed by Nakajima [0063].
Regarding Claim 10, (New) The combination of Nagaya, Bayless, and Nakajima discloses the manufacturing method according to claim 1.
Nakajima discloses: wherein the second deformation restriction layer (structure including glass substrate 3 and adhesive layer 2) comprises an adhesive layer (102) and a support substrate (3), FIG. 5, [0052].
Nakajima discloses that a method as taught prevents stress at the wafer peripheral ends and prevents chipping, cracking or breaking of the wafer [0063]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to prevent stress at the wafer peripheral ends and prevents chipping, cracking or breaking as disclosed by Nakajima [0063].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nagaya in view of Bayless, further in view of Nakajima, still further in view of Nomoto et al. (US20190207585A1; hereinafter Nomoto).
Regarding Claim 3, The combination of Nagaya, Bayless, and Nakajima discloses the manufacturing method according to claim 1.
Nagaya discloses the first deformation restriction layer (holding member 20, FIG. 1D, [0037]) and the second deformation restriction layer (auxiliary member 50, FIG. 1G, [0051]) arranged on the processed wafer 10.
The combination of Nagaya, Bayless, and Nakajima does not disclose “the second deformation includes a support substrate and the support substrate has a Young's modulus higher than that of the semiconductor substrate.”
In a similar art, Nomoto discloses a composite substrate, a method for producing the composite substrate, and an electronic device [0001].
Nomoto discloses a composite substrate 10 with a semiconductor substrate (functional substrate 12) and supporting substrate 14, FIG. 1, [0028]. Nomoto [0006], [0015] discloses an example of the functional substrate 12 includes silicon with a low Young's modulus of about 180 to 190 GPa. Nomoto [0017] discloses the support substrate 14 is made of sintered sialon body which has a moderate Young's modulus is 200 to 350 GPa. This indicates the Young’s modulus of the support substrate 14 (200 to 350 GPa) is higher than the Young’s modulus of the semiconductor substrate 12 (180 to 190 GPa).
The combination of Nagaya, Bayless, Nakajima, and Nomoto discloses: wherein at least one of the first deformation restriction layer (Nagaya: holding member 20, FIG. 1D, [0037]) and the second deformation restriction layer (Nagaya: auxiliary member 50, FIG. 1G, [0051]) includes a support substrate (Nomoto: supporting substrate 14), and
the support substrate (Nomoto: supporting substrate 14) has a Young's modulus higher than that of the semiconductor substrate (Nomoto: functional substrate 12), FIG. 1, [0015], [0017], [0028].
Nomoto discloses that a method as taught suppresses curling and cracking of the substrate [0017]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to the method in order to suppress curling and cracking of the substrate as disclosed by Nomoto [0017].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nagaya in view of Bayless, further in view of Nakajima, still further in view of Rieske et al. (US20210053148A1; hereinafter Rieske).
Regarding Claim 6, The combination of Nagaya, Bayless, and Nakajima discloses the manufacturing method according to claim 1.
In a similar art, Rieske discloses a method of manufacturing a semiconductor device [0001].
Nagaya discloses applying of the laser beam (laser beam L, FIG. 1F, [0043]) and removing a peripheral end of the first main surface of the semiconductor substrate (slit 16 is formed in the outer edge including the boundary of the chip formation region RA, FIG. 5, [0069]).
The combination of Nagaya, Bayless, and Nakajima does not disclose “further comprising: before the applying of the laser beam, removing a peripheral end of the first main surface of the semiconductor substrate so that a first part of a side surface of the semiconductor substrate adjacent to the first main surface is located on an inner side of the semiconductor substrate than a second part of the side surface of the semiconductor substrate adjacent to the second main surface in a planar direction of the semiconductor substrate.”
Rieske discloses: further comprising: before applying the laser beam (groove 190 is formed prior to laser treatment, [0113]), removing a peripheral end (forming groove 190) of the first main surface (101) of the semiconductor substrate (100), so that a first part of a side surface (193) of the semiconductor substrate (100) adjacent to the first main surface (101) is located on an inner side of the semiconductor substrate (193 is laterally inward in substrate 100) than a second part of the side surface (103) of the semiconductor substrate adjacent to the second main surface (102) in a planar direction of the semiconductor substrate (lateral direction of 100), FIG. 4A, [0127], [0130].
The combination of Nagaya, Bayless, Nakajima, and Rieske discloses: wherein in the applying of the laser beam, the laser beam is applied so that the plane extending at the predetermined depth inside the semiconductor substrate (Nagaya: laser beam L is applied to form the wafer transformation layer 15 at a predetermined depth L, FIG. 1F, [0043]) is positioned at the first part of the side surface (Rieske: 193).
Rieske discloses that a method as taught prevents edge chipping and reduces the risk of breakage of the substrate [0132]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to prevent edge chipping and reduces the risk of breakage of the substrate as disclosed by Rieske [0132].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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