DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/21/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Nagaya et al. (US20210327757A1; hereinafter Nagaya) in view of Inao et al. (US20130220554A1; hereinafter Inao).
Regarding Claim 1, Nagaya discloses a manufacturing method of a semiconductor device (manufacturing process of the semiconductor chip 100), FIGS. 1A-1J, [0033], comprising:
forming a first deformation restriction layer (holding member 20, FIG. 1D, [0037]) and a second deformation restriction layer (auxiliary member 50, FIG. 1G, [0051]) on a first main surface (10a) and a second main surface (10b) of a semiconductor substrate (processed wafer 10), the first main surface (10a) being opposite to the second main surface (10b), and the semiconductor substrate (10) having a device structure (element component 11) formed adjacent to the first main surface (10a), FIG. 1C, [0035].
applying a laser beam (laser beam L) through the second main surface (10b) of the semiconductor substrate (10) so as to irradiate a plane extending at a predetermined depth (predetermined depth L along the surface direction) inside of the semiconductor substrate (10) with the laser beam, FIG. 1F reproduced below, [0043]; and
peeling off a device layer (wafer is divided into the chip formation wafer 30 and the recycle wafer 40 at the wafer transformation layer 15) that is a part of the semiconductor substrate (10) including the first main surface (30a) and the device structure (11) from a remaining layer (40) of the semiconductor substrate along the plane irradiated with the laser beam (along the plane defined by the wafer transformation layer 15), FIG. 1G reproduced below, [0051].
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Nagaya: FIGS. 1F, 1G
Nagaya does not disclose “applying a laser beam through the second deformation restriction layer on the second main surface of the semiconductor substrate.”
In a similar art, Inao discloses a method of separating a substrate and a supporting member [0001].
Inao discloses: applying a laser beam (step (4)) through the second deformation restriction layer (supporting member) on the second main surface of the semiconductor substrate (supporting member-side surface of the wafer), FIG. 1, [0048].
Inao discloses that a method as taught prevents cracking and warpage in the wafer [0004]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nagaya’s method in order to prevent cracking and warpage as disclosed by Inao [0004].
Regarding Claim 2, The combination of Nagaya and Inao discloses the manufacturing method according to claim 1.
Nagaya discloses: wherein at least one of the first deformation restriction layer (20) and the second deformation restriction layer (50) includes an organic layer made of an organic material (20 and 50 include an adhesive made of ultraviolet curable resin which is an organic layer), [0051].
Regarding Claim 7, The combination of Nagaya and Inao discloses the manufacturing method according to claim 1.
Nagaya discloses: wherein the semiconductor substrate (10) is a nitride semiconductor substrate (processed wafer 10 includes Gallium Nitride wafer 1, [0034]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nagaya in view of Inao, further in view of Nomoto et al. (US20190207585A1; hereinafter Nomoto).
Regarding Claim 3, The combination of Nagaya and Inao discloses the manufacturing method according to claim 1.
Nagaya discloses: wherein at least one of the first deformation restriction layer (holding member 20, FIG. 1D, [0037]) and the second deformation restriction layer (auxiliary member 50, FIG. 1G, [0051]) arranged on the processed wafer 10.
The combination of Nagaya and Inao does not disclose “the second deformation includes a support substrate and the support substrate has a Young's modulus higher than that of the semiconductor substrate.”
In a similar art, Nomoto discloses a composite substrate, a method for producing the composite substrate, and an electronic device [0001].
Nomoto discloses a composite substrate 10 with a semiconductor substrate (functional substrate 12) and supporting substrate 14, FIG. 1, [0028]. Nomoto [0006], [0015] discloses an example of the functional substrate 12 includes silicon with a low Young's modulus of about 180 to 190 GPa. Nomoto [0017] discloses the support substrate 14 is made of sintered sialon body which has a moderate Young's modulus is 200 to 350 GPa. This indicates the Young’s modulus of the support substrate 14 (200 to 350 GPa) is higher than the Young’s modulus of the semiconductor substrate 12 (180 to 190 GPa).
The combination of Nagaya and Nomoto discloses: wherein at least one of the first deformation restriction layer (Nagaya: holding member 20, FIG. 1D, [0037]) and the second deformation restriction layer (Nagaya: auxiliary member 50, FIG. 1G, [0051]),
includes a support substrate (Nomoto: supporting substrate 14), and the support substrate has a Young's modulus higher than that of the semiconductor substrate (Nomoto: functional substrate 12), FIG. 1, [0015], [0017], [0028].
Nomoto discloses that a method as taught suppresses curling and cracking of the substrate [0017]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nagaya and Inao’s method in order to suppress curling and cracking of the substrate as disclosed by Nomoto [0017].
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Nagaya in view of Inao, further in view of Rieske et al. (US20210053148A1; hereinafter Rieske).
Regarding Claim 4, The combination of Nagaya and Inao discloses the manufacturing method according to claim 1.
Nagaya discloses: the forming of the first deformation restriction layer (20) and the second deformation restriction layer (50), FIGS. 1D, 1G, [0037], [0051].
The combination of Nagaya and Inao does not disclose “wherein
the semiconductor substrate has a curved end surface having a curved shape at a peripheral end of the second main surface, the second deformation restriction layer is formed so as to cover the curved end surface.”
In a similar art, Rieske discloses a method of manufacturing a semiconductor device [0001].
Rieske discloses: wherein the semiconductor substrate (100) has a curved end surface having a curved shape at a peripheral end of the second main surface (edge region 180 of the substrate includes a chamfer 185 on surface 102), FIG. 5A, [0137],
the second deformation restriction layer (adhesive layer 200 functions as the second deformation restriction layer) is formed so as to cover the curved end surface (chamfer 185), FIG. 8A, [0164].
Rieske discloses that a method as taught prevents chipping and reduces the occurrence of fractures at sharp edges of the substrate [0002]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nagaya and Inao’s method in order to prevent chipping and reducing the occurrence of fractures at sharp edges of the substrate as disclosed by Rieske [0002].
Regarding Claim 5, The combination of Nagaya, Inao, and Rieske discloses the manufacturing method according to claim 4.
Nagaya discloses: the forming of the first deformation restriction layer (20) and the second deformation restriction layer (50), FIGS. 1D, 1G, [0037], [0051],
The combination of Nagaya and Inao does not disclose “the second deformation restriction layer is formed so as not to cover a portion of a side surface of the semiconductor substrate, the portion corresponding to the plane extending at the predetermined depth and irradiated with the laser beam.”
Rieske discloses: the second deformation restriction layer (adhesive layer 200 functions as the second deformation restriction layer) is formed so as not to cover a portion of a side surface of the semiconductor substrate (a portion of 103 is not covered by 200), FIG. 8A, [0164].
The combination of Nagaya and Rieske discloses: a portion of the side surface of the semiconductor substrate (Rieske: portion of 103 not covered by 200, FIG. 8A, [0164]) corresponding to the plane, extending at the predetermined depth and irradiated with the laser beam (Nagaya: the plane defined by the wafer transformation layer 15 at a predetermined depth L irradiated with laser beam L, FIG. 1F, [0043]).
Rieske discloses that a method as taught prevents chipping and reduces the occurrence of fractures at sharp edges of the substrate [0002]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method in order to prevent chipping and reducing the occurrence of fractures at sharp edges of the substrate as disclosed by Rieske [0002].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nagaya in view of Inao, further in view of Hayashi et al. (JP2008053559A; hereinafter Hayashi).
Regarding Claim 6, The combination of Nagaya and Inao discloses the manufacturing method according to claim 1.
Nagaya discloses applying of the laser beam (laser beam L, FIG. 1F, [0043]) and removing a peripheral end of the first main surface of the semiconductor substrate (slit 16 is formed in the outer edge including the boundary of the chip formation region RA, FIG. 5, [0069]).
The combination of Nagaya and Inao does not disclose “further comprising:
before the applying of the laser beam, removing a peripheral end of the first main surface of the semiconductor substrate so that a first part of a side surface of the semiconductor substrate adjacent to the first main surface is located on an inner side of the semiconductor substrate than a second part of the side surface of the semiconductor substrate adjacent to the second main surface in a planar direction of the semiconductor substrate.”
In a similar art, Hayashi discloses a method for manufacturing a semiconductor device [0001].
Hayashi discloses: further comprising: removing a peripheral end of the first main surface of the semiconductor substrate (a part of semiconductor substrate 13 in the scribe region 3 is removed by etching, FIG. 9, [0074]), that a first part of a side surface of the semiconductor substrate adjacent to the first main surface (upper sidewall portion of substrate 13 adjacent to main surface 13t in the scribe region 3) is located on an inner side of the semiconductor substrate (13) than a second part of the side surface of the semiconductor substrate adjacent to the second main surface (lower sidewall portion of substrate 13 adjacent to second main surface 13r in the scribe region 3) in a planar direction of the semiconductor substrate, FIG. 9, [0070], [0074].
The combination of Nagaya and Hayashi discloses: wherein in the applying of the laser beam, the laser beam is applied so that the plane extending at the predetermined depth inside the semiconductor substrate (Nagaya: laser beam L is applied in the wafer transformation layer 15 at a predetermined depth L, FIG. 1F, [0043]) is positioned at the first part of the side surface (Hayashi: upper sidewall portion of substrate 13 adjacent to main surface 13t in the scribe region 3, FIG. 9, [0074]).
Hayashi discloses that a method as taught suppresses chipping of the wafer [0074]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nagaya and Inao’s method in order to suppress chipping of the wafer as disclosed by Hayashi [0074].
Conclusion
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899