DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 19 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species (B-E), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 25 April 2026.
Applicant’s election without traverse of Species A in the reply filed on 25 April 2026 is acknowledged.
Applicant’s election without traverse of Modification F1 in the telephone interview conducted with John C. Bacoch on 7 July 2026 is acknowledged.
Examiner notices that upon conducting a search for Species A, the Examiner was able to find prior art related to Species B, Species C, Species D and Species E and has therefore withdrawn the restriction requirement with respect to claim 19 upon which Species A is directed towards.
Examiner notices claim 9 appears to be directed to Device Modification F2. Therefore, Examiner has withdrawn claim 9 from consideration for examination. Applicant’s representative indicated in the telephone interview conducted on 7 July 2026 that Device Modification F1 is elected without traverse. Currently the Examiner believes claim 9 is drawn towards an unelected Device Modification (F2) as it requires a plurality of slits in the upper dam structure, as shown in at least Fig. 6A from which non-elected Device Modification F2 is drawn.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 21 November 2023 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Satoru Takaku (US 2022/0028815 A1; hereinafter “Takaku”).
Regarding Claim 1, Takaku teaches a semiconductor package comprising:
a substrate (11, Fig. 5, para [0019] describes a substrate 11) including a passivation layer (16a, Fig. 5, para [0056] describes a solder resist layer 16a on the substrate 11);
a semiconductor chip mounted on the substrate (30, Fig. 5, para [0018] describes a semiconductor chip 30 mounted on the substrate 11);
an underfill material layer between the semiconductor chip and the substrate (35, Fig. 5, para [0023] describes a resin layer 35 which may be an underfill between the semiconductor chip 30 and the substrate 11 of a wiring board 10); and
a dam structure on the substrate and surrounding the semiconductor chip (16b and 17, Fig. 4, para [0052] describes a projecting portion 17 of solder resist functioning as a dam surrounding at least two sides of the semiconductor chip 30 in a horizontal direction),
wherein a lower portion of the dam structure is in contact with the passivation layer (16a and 16b, Fig. 5, para [0057] describes forming solder resist 16b including dam protruding portion 17 on passivation layer 16a) and is formed of a material that is the same as a material forming the passivation layer (16a and 16b, Fig. 5, para [0058] describes wherein passivation layer 16a and dam structure 16b and 17 may be formed of a same solder resist material), and
an upper surface of the dam structure includes a first segment at a first vertical level (FVL, annotated Fig. 5 depicts a first segment of an upper surface of the dam structure 16b at a first vertical level FVL) and a second segment at a second vertical level different from the first vertical level (SVL, annotated Fig. 5 depicts a second segment of an upper surface of the dam structure 16b at a second vertical level SVL different from the first vertical level SVL).
PNG
media_image1.png
422
726
media_image1.png
Greyscale
Regarding Claim 2, Takaku teaches the semiconductor package of claim 1, wherein the lower portion of the dam structure and the passivation layer are formed of a solder resist (16a and 16b, Fig. 5, para [0058] describes wherein passivation layer 16a and dam structure 16b and 17 may be formed of a same solder resist material).
Regarding Claim 12, Takaku teaches the semiconductor package of claim 1, further comprising
chip connection bumps between the semiconductor chip and the substrate (31, Fig. 5, para [0019] describes metal bumps 31 connected to the controller chip 30 and metal pads 14 connected to the substrate 11),
wherein the underfill material layer is in contact with the chip connection bumps and the dam structure (35, Fig. 5, para [0023] describes wherein the underfill material layer 35 covers the connection bumps 31 and is in contact with dam structure 16b and 17).
Claims 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Minsoo Kim (US 2021/0111160 A1; hereinafter “Kim”).
Regarding Claim 13, Kim teaches a semiconductor package comprising:
a substrate (500, Fig. 4, para [0041] describes a base substrate 500);
a semiconductor chip mounted on the substrate (100, Fig. 4, para [0018] describes a first semiconductor chip mounted on substrate 500);
an underfill material layer between the semiconductor chip and the substrate (150, Fig. 4, para [0020] describes an NCF disposed between the substrate 500 and the first semiconductor chip 100); and
a dam structure (604, Fig. 4, para [0079] describes a dam structure 604) including a ring-shaped lower dam surrounding the semiconductor chip (LD, annotated Fig. 4 and Fig. 2B, para [0068] describes wherein a lower portion LD of the dam structure 602, of a same shape as dam structure 604, is disposed in a ring shape facing each side surface of the first semiconductor chip 100) and an upper dam on the lower dam (UD, annotated Fig. 4 depicts an upper dam UD of the dam structure 604),
wherein the upper dam includes eaves covering a portion of a gap between the lower dam and the semiconductor chip (604, annotated Fig. 4, para [0080] describes wherein the upper dam UD includes bent portions bent towards the first semiconductor chip 100 resulting in eaves covering a portion of a gap between the lower dam UD and the semiconductor chip 100).
PNG
media_image2.png
548
647
media_image2.png
Greyscale
Regarding Claim 14, Kim teaches the semiconductor package of claim 13, wherein the upper dam extends along a portion of the lower dam (UD and LD, annotated Fig. 4 depicts wherein the upper dam UD extends along at least an upper portion of the lower dam LD).
Regarding Claim 15, Kim teaches the semiconductor package of claim 13, wherein the lower dam and the upper dam are formed of a solder resist (600 and 604, Fig. 4, para [0052] describes wherein the dam structure 600, similar to dam structure 604, may include a material similar to a material of a non-conductive film 150 which may be thermocurable resin as described in para [0045] wherein a thermocurable resin of a non-conductive film may be a solder resist material).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 6 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Satoru Takaku (US 2022/0028815 A1; hereinafter “Takaku”) in view of Chun-Lin Lu et al. (US 2014/0160688 A1; hereinafter “Lu”).
Regarding Claim 3, Takaku teaches the semiconductor package of claim 1,
wherein the dam structure (16b and 17, Fig. 5) includes
a lower dam formed of the same material as that of the passivation layer (16a and 16b, Fig. 5, para [0058] describes wherein passivation layer 16a and dam structure 16b and 17 may be formed of a same solder resist material).
Takaku fails to explicitly disclose wherein the dam structure includes a lower dam having a ring-shape surrounding the semiconductor chip and an upper dam disposed on the lower dam and extending along a portion of the lower dam.
However, Lu teaches a similar semiconductor package,
wherein the dam structure (113 and 114, Fig. 1(b), para [0030] describes a dam structure 113 and 114) includes
a lower dam having a ring-shape surrounding the semiconductor chip (113, Fig. 2(a), para [0039] describes wherein a lower dam 113 surrounds a die 131 in a ring shape as shown in Fig. 2(a)) and
an upper dam disposed on the lower dam and extending along a portion of the lower dam (114, Fig. 1(b), para [0030] describes an upper dam 114 formed on an upper portion of the lower dam 113).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Takaku with Lu to further disclose a semiconductor package wherein the dam structure includes a lower dam having a ring-shape surrounding the semiconductor chip and an upper dam disposed on the lower dam and extending along a portion of the lower dam in order to provide the advantage of providing a second dam structure which may be high enough to stop the overflow of an underfill material which could cause undesirable effects if it covers conductive connection points outside of the ring shaped dam region (Lu, para [0035]).
Regarding Claim 6, the combination of Takaku and Lu teaches the semiconductor package of claim 3, wherein the lower dam is formed of a different material than a material forming the upper dam (Lu, 113 and 114, Fig. 1(b), para [0030] describes wherein upper dam 114 may be formed of a non-conductive material and para [0028] describes wherein the lower dam 113 may comprise a conductive metal material wherein a conductive metal material and a non-conductive material are different).
Regarding Claim 10, Takaku discloses all the limitations of claim 1.
Takaku fails to explicitly disclose the semiconductor package of claim 1, wherein a first distance between the first segment of the upper surface of the dam structure and an upper surface of the substrate is between about 20 μm and about 50 μm, a second distance between the second segment of the upper surface of the dam structure and the upper surface of the substrate is greater than the first distance, the difference between the second distance and the first distance is between about 10 μm and about 100 μm.
However, Lu teaches a similar semiconductor package,
wherein a first distance between the first segment of the upper surface of the dam structure and an upper surface of the substrate is between about 20 μm and about 50 μm (113, Fig. 1(b) and Fig. 1(c), para [0029] describes wherein a dam structure 113 which may be disposed on an upper surface of an interposer 100 including substrate 101 may have a height of about 20 μm to about 30 μm resulting in a first distance between a first segment of the upper surface of the dam structure 113 and an upper surface of the substrate being between about 20 μm and about 50 μm),
a second distance between the second segment of the upper surface of the dam structure and the upper surface of the substrate is greater than the first distance (114, Fig. 1(b), para [0030] describes an upper dam structure 114 disposed on dam structure 113 wherein a second distance between the second segment of the upper surface of the upper dam structure 114 and the interposer 100 comprising substrate 101 is greater than the first distance).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Takaku with Lu to further disclose a semiconductor package wherein a first distance between a first segment of an upper surface of a dam structure and an upper surface of a substrate is between about 20 μm and about 50 μm and a second distance between a second segment of a upper surface of the dam structure and an upper surface of the substrate is greater than the first distance in order to provide the advantage of providing a flexible dam structure so that the height and volume of an underfill material used in the packaging process can be adjusted according to the needs of the device (Lu, para [0035]).
The combination of Takaku and Lu fails to explicitly disclose wherein the difference between the second distance and the first distance is between about 10 μm and about 100 μm.
However, Lu teaches in the disclosure of their invention wherein the height of the lower dam (113) may be about the same size as a connector ball (129) or as much as 1/10 of the size of the diameter of the connector which may have a diameter of approximately 100 μm (para [0029]). As shown in Fig. 3, the combination of the lower dam structure (113) and the upper dam structure (114) are of a same height as the connector ball (129) formed between a first substrate structure (100) and a second substrate structure (301).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size lower dam structures (113) and upper dam structures (114) wherein each may be from a range of 1/10 the height of a connector (129) to a full height of up to 200 μm, resulting in a first distance which may be approximately 60 μm and a second distance which may be 140 μm wherein a resulting distance of 80 μm is between about 10 μm and about 100 μm, in order to provide the advantage of providing a dam structure that prevents underfill material from flowing out over the dam structure which would result in undesirable effects in surrounding electrical components in the semiconductor package (Lu, para [0034] – para [0035], see MPEP 2144.04 (IV)(A) and MPEP 2144.05 (II)(A)(B)).
Regarding Claim 11, Takaku discloses all the limitations of claim 1.
Takaku fails to explicitly disclose the semiconductor package of claim 1, wherein the dam structure includes a sidewall and a width of the sidewall in a first direction parallel to an upper surface of the substrate is between about 40 μm and about 200 μm.
However, Lu teaches a similar semiconductor package, wherein the dam structure includes a sidewall (113, Fig. 1(b) and Fig. 1(c), para [0029] describes a dam structure including dam 113 which has a sidewall as viewed in Fig. 1(b) and Fig. 1(c)) and a width of the sidewall in a first direction parallel to an upper surface of the substrate is between about 40 μm and about 200 μm (113, Fig. 1(b) and Fig. 1(c), para [0029] describes wherein a width of the dam 113 may be around 100 μm which falls within the range of 40 μm to about 200 μm).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Takaku with Lu to further disclose a semiconductor package wherein a dam structure includes a sidewall and a width of the sidewall in a first direction parallel to an upper surface of the substrate is between about 40 μm and about 200 μm in order to provide the well-known advantage of providing a dam structure which is wide enough to support an underfill flow process while maintaining a size similar to that of surrounding connector components enabling electrical connections to be made to surrounding components without interfering and further reducing the size of the semiconductor package increasing density therefore decreasing manufacturing costs.
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Satoru Takaku (US 2022/0028815 A1; hereinafter “Takaku”) in view of Lutz Rissing et al. (US 2003/0173655 A1; hereinafter “Rissing”).
Regarding Claim 3, Takaku teaches the semiconductor package of claim 1,
wherein the dam structure (16b and 17, Fig. 5) includes
a lower dam formed of the same material as that of the passivation layer (16a and 16b, Fig. 5, para [0058] describes wherein passivation layer 16a and dam structure 16b and 17 may be formed of a same solder resist material).
Takaku fails to explicitly disclose wherein the dam structure includes a lower dam having a ring-shape surrounding the semiconductor chip and an upper dam disposed on the lower dam and extending along a portion of the lower dam.
However, Rissing teaches a similar semiconductor package,
wherein the dam structure (30, Fig. 1, para [0024] describes a dam structure 30) includes
a lower dam having a ring-shape surrounding the semiconductor chip (30 and 31, Fig. 1 and Fig. 2, para [0024] and para [0031] describe wherein the dam structure 30 may have a lower dam 31 disposed in a ring shape surrounding a semiconductor component 20 as shown in Fig. 2) and
an upper dam disposed on the lower dam and extending along a portion of the lower dam (32, Fig. 1, para [0031] describes an upper dam layer 32 disposed on the lower dam 31 and extending along an upper portion of the lower dam 31).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Takaku with Rissing to further disclose a semiconductor package wherein the dam structure includes a lower dam having a ring-shape surrounding the semiconductor chip and an upper dam disposed on the lower dam and extending along a portion of the lower dam in order to provide the advantage of providing a dam structure which may be used to adjust the necessary level of an encapsulating compound without taking up too much surface area on a substrate (Rissing, para [0025]).
Regarding Claim 5, the combination of Takaku and Rissing teaches the semiconductor package of claim 3, wherein the lower dam and the upper dam are formed of the same material as each other (Rissing, 31 and 32, Fig. 1, para [0031] describes wherein the lower dam 31 and upper dam 32 are made of a same dam material).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Satoru Takaku (US 2022/0028815 A1; hereinafter “Takaku”) in view of Chun-Lin Lu et al. (US 2014/0160688 A1; hereinafter “Lu”) and in further view of Chang-Lin Yeh (US 2019/0139786 A1; hereinafter “Yeh”).
Regarding Claim 4, the combination of Takaku and Lu teaches the semiconductor package of claim 3,
wherein the lower dam (Lu, Fig. 1(b), para [0027] describes a lower dam 113 formed on a passivating layer) includes a first lower sidewall facing a first side of the semiconductor chip (Lu, FLS, annotated Fig. 2(a) depicts wherein the lower dam 113 includes a first lower sidewall FLS facing a first side of the semiconductor chip 131), a second lower sidewall facing a second side of the semiconductor chip (Lu, SLS, annotated Fig. 2(a) depicts wherein the lower dam 113 includes a second lower sidewall SLS facing a second side of the semiconductor chip 131), a third lower sidewall facing a third side of the semiconductor chip (Lu, TLS, annotated Fig. 2(a) depicts wherein the lower dam 113 includes a third lower sidewall TLS facing a third side of the semiconductor chip 131), and a fourth lower sidewall facing a fourth side of the semiconductor chip (Lu, FRLS, annotated Fig. 2(a) depicts wherein the lower dam 113 includes a fourth lower sidewall FRLS facing a fourth side of the semiconductor chip 131),
the upper dam extends along at least one of the first lower sidewall, the second lower sidewall, and the third lower sidewall of the lower dam (Lu, 114, Fig. 1(b), para [0030] describes wherein upper dam 114 may be formed on the lower dam 113 wherein Fig. 1(b) depicts upper dam 114 being formed on at least one of the first, second, or third lower sidewalls).
PNG
media_image3.png
348
448
media_image3.png
Greyscale
Takaku and Lu fail to explicitly disclose wherein the upper dam does not extend along the fourth lower sidewall of the lower dam.
However, Yeh teaches a similar semiconductor package wherein the upper dam (10t1 and 12, Fig. 1C and Fig. 1E, para [0029] describes a barrier element comprising an upper dam portion 10t1 as shown in at least Fig. 1E as being an upper dam portion along trace 10t) does not extend along the fourth lower sidewall of the lower dam (10t2 and FLS2, annotated Fig. 1C and Fig. 1E, para [0031] describes wherein an upper dam portion 10t1 comprising barrier element 12 does not extend along a fourth lower sidewall FLS2 of a lower dam portion 10t2 comprising barrier element 12 that is facing a fourth side of a semiconductor chip 11).
PNG
media_image4.png
510
786
media_image4.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Takaku and Lu with Yeh to further disclose a semiconductor package wherein an upper dam does not extend along a fourth lower sidewall of a lower dam in order to provide the advantage of providing a dam structure which may avoid the bleeding out of an underfill material which would occupy a space that is supposed to accommodate other components on a substrate leading to undesirable device characteristics and decreased device reliability (Yeh, para [0029] and para [0030]).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Satoru Takaku (US 2022/0028815 A1; hereinafter “Takaku”) in view of Chun-Lin Lu et al. (US 2014/0160688 A1; hereinafter “Lu”) and in further view of Minsoo Kim (US 2021/0111160 A1; hereinafter “Kim”).
Regarding Claim 7, the combination of Takaku and Lu discloses all the limitations of claim 3.
Takaku and Lu fail to explicitly disclose the semiconductor package of claim 3, wherein the upper dam includes a lower sidewall, the upper dam includes an upper sidewall, and a width of the upper sidewall in a first direction parallel to an upper surface of the substrate is greater than a width of the lower sidewall in the first direction.
However, Kim teaches a similar semiconductor package, wherein the upper dam includes a lower sidewall (UPLS, annotated Fig. 4 II, para [0079] describes a dam structure 604 wherein the dam structure 604 comprises an upper dam including an upper dam lower sidewall UPLS), the upper dam includes an upper sidewall (UPUS, annotated Fig. 4 II, para [0079] describes a dam structure 604 wherein the dam structure 604 comprises an upper dam including an upper dam upper sidewall UPUS), and a width of the upper sidewall in a first direction parallel to an upper surface of the substrate is greater than a width of the lower sidewall in the first direction (UPUS and UPLS, annotated Fig. 4 II, para [0080] describes wherein the dam structure 604 may include a bent portion of which an upper portion is perpendicularly bent wherein said portion comprises the upper dam upper sidewall UPUS resulting in a portion formed in an X direction which has a width greater than width of the upper dam lower sidewall UPLS in the X direction as shown in annotated Fig. 4 II).
PNG
media_image5.png
577
616
media_image5.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Takaku and Lu with Kim to further disclose a semiconductor package wherein a width of an upper sidewall of an upper dam in a first direction parallel to an upper surface of the substrate is greater than a width of a lower sidewall of an upper dam in the first direction in order to provide the well-known advantage of helping to prevent an underfill material layer from flowing beyond a dam structure during an underfill forming process which would result in underfill material reaching surrounding electrical components resulting in reduced device reliability and undesirable electrical characteristics.
Regarding Claim 8, the combination of Takaku and Lu discloses all the limitations of claim 3.
Takaku and Lu fail to explicitly disclose the semiconductor package of claim 3, wherein the upper dam further includes eaves extending laterally from an inner surface of the lower dam toward the semiconductor chip to cover a portion of a gap between the lower dam and the semiconductor chip.
However, Kim teaches a similar semiconductor package, wherein the upper dam further includes eaves extending laterally from an inner surface of the lower dam toward the semiconductor chip to cover a portion of a gap between the lower dam and the semiconductor chip (UD, LD and 604, annotated Fig. 4, para [0080] describes wherein the upper dam UD includes bent portions bent towards the first semiconductor chip 100 resulting in eaves covering a portion of a gap between the lower dam UD and the semiconductor chip 100 and extending laterally from an inner surface of the lower dam LD)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Takaku and Lu with Kim to further disclose a semiconductor package wherein an upper dam further includes eaves extending laterally from an inner surface of a lower dam toward a semiconductor chip to cover a portion of a gap between the lower dam and the semiconductor chip in order to provide the well-known advantage of helping to prevent an underfill material layer from flowing beyond a dam structure during an underfill forming process which would result in underfill material reaching surrounding electrical components resulting in reduced device reliability and undesirable electrical characteristics.
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Minsoo Kim (US 2021/0111160 A1; hereinafter “Kim”) in view of Satoru Takaku (US 2022/0028815 A1; hereinafter “Takaku”).
Regarding Claim 16, Kim disclose the semiconductor package of claim 13,
wherein the substrate (500, Fig. 6, para [0041] describes a base substrate 500) includes
a base layer (510, Fig. 6, para [0041] describes a substrate body part 510);
an upper passivation layer on an upper surface of the base layer (Fig. 6, para [0041] describes wherein a solder resist layer may be formed on an upper surface of the base layer 510); and
a lower passivation layer on a lower surface of the base layer (Fig. 6, para [0041] describes wherein a solder resist layer may be formed on a lower surface of the base layer 510),
Kim fails to explicitly disclose wherein the lower dam is in contact with the upper passivation layer and is formed of the same material as the material forming the upper passivation layer.
However, Takaku teaches a similar semiconductor package wherein the lower dam is in contact with the upper passivation layer (16a and 16b, Fig. 5, para [0058] describes an upper passivation layer 16a upon which a dam structure 16b and 17 is disposed) and is formed of the same material as the material forming the upper passivation layer (16a and 16b, Fig. 5, para [0058] describes wherein the upper passivation layer 16a and dam structure 16b and 17 may be formed of a same solder resist material).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kim with Takaku to further disclose a semiconductor package wherein a lower dam is in contact with an upper passivation layer and is formed of a same material as the material forming an upper passivation layer in order to provide the well-known advantage of simplifying a manufacturing process and reducing manufacturing costs by using a same material for components disposed in subsequent steps in a semiconductor package.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chun-Lin Lu et al. (US 2014/0160688 A1; hereinafter “Lu”) in view of Satoru Takaku (US 2022/0028815 A1; hereinafter “Takaku”).
Regarding Claim 17, Lu teaches a semiconductor package comprising:
a substrate (100 and 101, Fig. 1(b), para [0012] describes an interposer 100 with a substrate 101) including a base layer (101, Fig. 1(b), para [0012] describes a base substrate layer 101 of an interposer 101), connection pads on the base layer (117, Fig. 1(b), para [0030] describes contact pads 117 on the base layer 101), and a passivation layer on the base layer (Fig. 1(b), para [0016] describes wherein a passivation layer may be formed on the substrate 101);
chip connection bumps connected to the connection pads through openings of the passivation layer (125, Fig. 1(b), para [0030] describes connectors 125 contacting and connected to the connection pads 117 wherein the connectors are through openings in the passivation layer in order to form an electrical connection);
a semiconductor chip connected to the chip connection bumps (131, Fig. 1(b), para [0030] describes wherein a semiconductor die 131 is connected to the chip connection bumps 125);
an underfill material layer provided between the semiconductor chip and the substrate and surrounding the chip connection bumps (123, Fig. 1(b), para [0030] describes wherein an underfill 123 is provided between the semiconductor chip 131 and the substrate 100 and further surrounding the connection bumps 125 on at least a side surface); and
a dam structure on the substrate and surrounding the semiconductor chip (113 and 114, Fig. 1(b) and Fig. 2(a), para [0027] describes a dam structure 113 and 114 on the substrate 100 and surrounding the semiconductor chip 131 as shown in Fig. 2(a)), the dam structure including a lower dam attached to the passivation layer (113, Fig. 1(b), para [0027] describes wherein a lower portion of the dam 113 may be formed on the passivation layer) and an upper dam on the lower dam (114, Fig. 1(b), para [0030] describes an upper dam structure 114 formed on the lower dam 113),
wherein an upper surface of the dam structure includes a plurality of segments at different vertical levels (113 and 114, Fig. 1(b), para [0030] describes dam portion 113 and 114 wherein an upper surface of the lower dam 113 includes a first segment at a first vertical level and an upper surface of the upper dam 114 includes a second segment at a different vertical level),
wherein the lower dam (Fig. 1(b), para [0027] describes the lower dam 113) includes a first lower sidewall facing a first side of the semiconductor chip (FLS, annotated Fig. 2(a) depicts wherein the lower dam 113 includes a first lower sidewall FLS facing a first side of the semiconductor chip 131), a second lower sidewall facing a second side of the semiconductor chip (SLS, annotated Fig. 2(a) depicts wherein the lower dam 113 includes a second lower sidewall SLS facing a second side of the semiconductor chip 131), a third lower sidewall facing a third side of the semiconductor chip (TLS, annotated Fig. 2(a) depicts wherein the lower dam 113 includes a third lower sidewall TLS facing a third side of the semiconductor chip 131), and a fourth lower sidewall facing a fourth side of the semiconductor chip (FRLS, annotated Fig. 2(a) depicts wherein the lower dam 113 includes a fourth lower sidewall FRLS facing a fourth side of the semiconductor chip 131),
the upper dam extends along at least one of the first lower sidewall, the second lower sidewall, and the third lower sidewall of the lower dam (114, Fig. 1(b), para [0030] describes wherein upper dam 114 may be formed on the lower dam 113 wherein Fig. 1(b) depicts upper dam 114 being formed on at least one of the first, second, or third lower sidewalls).
Lu fails to explicitly disclose wherein the lower dam, the upper dam, and the passivation layer include the same material as each other.
However, Takaku teaches a similar semiconductor package, wherein the lower dam (16b, Fig. 5, para [0058] describes a solder resist layer 16b forming a lower dam structure), the upper dam (17 and 16, Fig. 5, para [0052] describes a projecting portion 17 of a solder resist material 16 that forms an upper dam structure), and the passivation layer include the same material as each other (16a, Fig. 5, para [0058] describes a solder resist layer 16a deposited over the substrate wherein the passivation layer 16a, the lower dam 16b and upper dam 16 and 17 are all formed of a same solder resist material as described in para [0058]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lu with Takaku to further disclose a semiconductor package wherein a lower dam, an upper dam and a passivation layer include the same material as each other in order to provide the well-known advantage of simplifying a manufacturing process and reducing manufacturing costs by using a same material for components disposed in subsequent steps in a semiconductor package.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chun-Lin Lu et al. (US 2014/0160688 A1; hereinafter “Lu”) in view of Satoru Takaku (US 2022/0028815 A1; hereinafter “Takaku”) and in further view of Lutz Rissing et al. (US 2003/0173655 A1; hereinafter “Rissing”).
Regarding Claim 18, the combination of Lu and Takaku teaches the semiconductor package of claim 17, wherein an upper surface of the upper dam is at a first vertical level (Lu, FVL2, annotated Fig. 1(b) depicts wherein an upper surface of the upper dam 114 is at a first vertical level FVL2), an upper surface of the lower dam is at a second vertical level (Lu, SVL2, annotated Fig. 1(b) depicts wherein an upper surface of the lower dam 113 is at a second vertical level SVL2), the first vertical level is higher than the second vertical level (Lu, FVL2 and SVL2, annotated Fig. 1(B) depicts wherein the first vertical level FVL2 is higher than the second vertical level SVL2), and the upper dam includes a first upper sidewall extending along the first lower sidewall of the lower dam (Lu, FUS, annotated Fig. 1(b) depicts a first upper sidewall FUS of the upper dam 114 extending along the first lower sidewall FLS of the lower dam 113), and a third upper sidewall extending along the third lower sidewall of the lower dam (Lu, TUS, annotated Fig. 1(b) depicts a third upper sidewall TUS of the upper dam 114 extending along the third lower sidewall TLS of the lower dam 113).
PNG
media_image6.png
283
609
media_image6.png
Greyscale
Lu teaches wherein the upper dam is placed on the lower dam (para [0030]).
Lu and Takaku fails to explicitly disclose wherein the upper dam includes a second upper sidewall extending along the second lower sidewall of the lower dam.
However, Rissing teaches a similar semiconductor package, wherein the upper dam (32, Fig. 1, para [0031] describes an upper dam layer 32) includes a second upper sidewall extending along the second lower sidewall of the lower dam (30 and 31, Fig. 1 and Fig. 2, para [0031] describes wherein the dam structure 30 includes a lower dam 31 and the upper dam 32 extending along a first through fourth sidewall facing a semiconductor component 20 wherein the upper dam 32 therefore includes a second upper sidewall extending along a corresponding second lower sidewall of the lower dam 31).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Lu and Takaku with Rissing to further disclose a semiconductor package wherein an upper dam includes a second upper sidewall extending along a second lower sidewall of a lower dam in order to provide the advantage of providing a dam structure with a defined adjustment of a desired ratio of dam height and dam width so as to provide a dam structure which is stable and does not require unwanted enlargement of the substrate surface (Rissing, para [0031] and para [0034]).
Regarding Claim 19, the combination of Lu, Takaku and Rissing teaches the semiconductor package of claim 18, wherein the upper dam (Rissing, 32, Fig. 1, para [0031] describes the upper dam layer 32) further includes a fourth upper sidewall on a portion of the fourth lower sidewall of the lower dam (Rissing, 30 and 31, Fig. 1 and Fig. 2, para [0031] describes wherein the dam structure 30 includes a lower dam 31 and the upper dam 32 extending along a first through fourth sidewall facing a semiconductor component 20 wherein the upper dam 32 therefore includes a fourth upper sidewall extending along a corresponding fourth lower sidewall of the lower dam 31 as shown in Fig. 2).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chun-Lin Lu et al. (US 2014/0160688 A1; hereinafter “Lu”) in view of Satoru Takaku (US 2022/0028815 A1; hereinafter “Takaku”) and in further view of Minsoo Kim (US 2021/0111160 A1; hereinafter “Kim”).
Regarding Claim 20, the combination of Lu and Takaku discloses all the limitations of claim 17.
Takaku and Lu fail to explicitly disclose the semiconductor package of claim 17, wherein the upper dam further includes eaves extending laterally from an inner surface of the upper dam toward the semiconductor chip to cover a portion of a gap between the lower dam and the semiconductor chip.
However, Kim teaches a similar semiconductor package, wherein the upper dam further includes eaves extending laterally from an inner surface of the lower dam toward the semiconductor chip to cover a portion of a gap between the lower dam and the semiconductor chip (UD, LD and 604, annotated Fig. 4, para [0080] describes wherein the upper dam UD includes bent portions bent towards the first semiconductor chip 100 resulting in eaves covering a portion of a gap between the lower dam UD and the semiconductor chip 100 and extending laterally from an inner surface of the lower dam LD)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Takaku and Lu with Kim to further disclose a semiconductor package wherein an upper dam further includes eaves extending laterally from an inner surface of a lower dam toward a semiconductor chip to cover a portion of a gap between the lower dam and the semiconductor chip in order to provide the well-known advantage of helping to prevent an underfill material layer from flowing beyond a dam structure during an underfill forming process which would result in underfill material reaching surrounding electrical components resulting in reduced device reliability and undesirable electrical characteristics.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights