DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 11/21/23. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-7 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4-5 and 7 recite the term “about”. The term "about" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “About” is defined as "almost or nearly—used to indicate that a number, amount, time, etc., is not exact or certain” (see Merriam Webster online dictionary). The term “about” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “about” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claims are rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention. Claims 5-7 inherit the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, rejections based on their dependencies on claim 4.
Regarding claim 14, the term “substantially” in claim 14 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term substantial is defined as “being largely but not wholly that which is specified.” The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” near the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claims are rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (U.S. 2022/0415809 A1; “Kim”).
Regarding claim 1, Kim discloses a semiconductor package, comprising:
A substrate (100, Fig. 1) including a chip region (portion of 100 under 200, Fig. 1) and an edge region (left and right lateral portions of 100 not under 200, Fig. 1) extending around the chip region ([0015]);
A plurality of film wirings (104 within portion of 100 under 200, Fig. 1) on the substrate in the chip region ([0015]);
An input wiring (104 on left lateral portion of 100 not under 200, Fig. 1) and an output wiring (104 on right lateral portion of 100 not under 200, Fig. 1) on the substrate in the edge region and extending to the chip region in a first direction parallel to an upper surface of the substrate ([0015]); and
A semiconductor chip (200, Fig. 1) on the substrate in the chip region and electrically connected to the input wiring and the output wiring ([0015]),
Wherein the substrate (100, Fig. 1) includes at least one through hole (VH1, Fig. 1) extending through the substrate in a second direction perpendicular to the first direction ([0018]-[0019]), and the at least one through hole (VH1, Fig. 1) is located between the plurality of film wirings (104 within portion of 100 under 200, Fig. 1).
Regarding claim 8, Kim discloses a width of the at least one through hole (VH1, Fig. 1) in the first direction is constant as the through hole extends in the second direction from the upper surface of the substrate to a lower surface of the substrate.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al. (U.S. 2020/0273804 A1; “Jeon”).
Regarding claim 1, Jeon discloses a semiconductor package, comprising:
A substrate (110, Fig. 15) including a chip region (portion of 110 under 130, Fig. 15) and an edge region (left and right lateral portions of 110 not under 130, Fig. 15) extending around the chip region ([0020]);
A plurality of film wirings (uppermost 114 portion of 110 under 130, Fig. 15) on the substrate in the chip region ([0025]);
An input wiring (uppermost 114 on left lateral portion of 110 not under 130, Fig. 15) and an output wiring (uppermost 114 on right lateral portion of 110 not under 130, Fig. 15) on the substrate in the edge region and extending to the chip region in a first direction parallel to an upper surface of the substrate ([0025]); and
A semiconductor chip (130, Fig. 15) on the substrate in the chip region and electrically connected to the input wiring and the output wiring ([0031]),
Wherein the substrate includes at least one through hole (holes containing uppermost 114, Fig. 15) extending through the substrate in a second direction perpendicular to the first direction, and the at least one through hole is located between the plurality of film wirings (uppermost 114 portion of 110 under 130, Fig. 15) ([0023]).
Regarding claim 2, Jeon discloses a width of the at least one through hole (holes containing uppermost 114, Fig. 15) in the first direction decreases as the through hole extends in the second direction from the upper surface of the substrate to a lower surface of the substrate.
Regarding claim 3, Jeon discloses a side surface of the at least one through hole (holes containing uppermost 114, Fig. 15) includes a forward taper inclined surface in a cross-sectional view.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (U.S. 2020/0273804 A1; “Jeon”) as applied to claim 1 above.
Regarding claim 4, Jeon discloses the least one through hole (holes containing uppermost 114, Fig. 15) have a second (lower) width smaller than a first (upper) width (Fig. 15) but does not disclose the ratio of the second width to the first width is 1:2 to 1:10. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select second and first widths such that a ratio between the second width to the first width is between 1:2 and 1:10, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 5, Jeon discloses the least one through hole (holes containing uppermost 114, Fig. 15) has a first (upper) width (Fig. 15) but does not disclose it is between 20 µm and 100 µm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select a first width between 20 µm and 100 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 6, Jeon discloses spacing between adjacent pairs of the plurality of film wirings (uppermost 114 portion of 110 under 130, Fig. 15) but does not disclose it is equal to or greater than the first width. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select spacings between adjacent pairs of the plurality of film wirings to be equal to or greater than the first width, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 7, Jeon discloses spacing between adjacent pairs of the plurality of film wirings (uppermost 114 portion of 110 under 130, Fig. 15) but does not disclose it is between 50 µm and 100 µm. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select a spacing between adjacent pairs of the plurality of film wirings to be between 50 µm and 100 µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2022/0415809 A1; “Kim”) in view of Takamichi et al. (U.S. 6,054,755; “Takamichi”).
Regarding claim 11, Kim discloses a semiconductor package, comprising:
A substrate (100, Fig. 1) including a chip region (portion of 100 under 200, Fig. 1) and an edge region (left and right lateral portions of 100 not under 200, Fig. 1) extending around the chip region ([0015]);
A plurality of film wirings (104 within portion of 100 under 200, Fig. 1) on the substrate in the chip region ([0015]);
An input wiring (104 on left lateral portion of 100 not under 200, Fig. 1) and an output wiring (104 on right lateral portion of 100 not under 200, Fig. 1) on the substrate in the edge region and extending to the chip region in a first direction parallel to an upper surface of the substrate ([0015]);
A semiconductor chip (200, Fig. 1) on the substrate in the chip region and electrically connected to the input wiring and the output wiring ([0015]); and
An under-fill layer (500, Fig. 1) between the substrate (100, Fig. 1) and the semiconductor chip (200, Fig. 1),
Wherein the substrate (100, Fig. 1) includes a through hole (VH1, Fig. 1) extending through the substrate in a second direction perpendicular to the first direction, the through hole (VH1, Fig. 1) is between the plurality of film wirings (104 within portion of 100 under 200, Fig. 1), and the under-fill layer (500, Fig. 1) at least partially fills the through hole (VH1, Fig. 1).
Yet, Kim does not disclose the through hole is part of a plurality of through holes. However, Takamichi discloses a through hole is part of a plurality of through holes (col 4, lines 8-10). This has the advantage of providing additional venting holes for the package which decreases the occurrence of voids and improves package reliability. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Kim with a plurality of through holes, as taught by Takamichi, so as to improve package reliability.
Allowable Subject Matter
Claims 18-20 are allowed.
Claim 18 contains allowable subject matter because of the limitation of an under-fill layer at least partially filling a gap region between the substrate and the semiconductor chip, wherein the substrate includes a plurality of through holes extending through the substrate in a second direction perpendicular to the first direction, the plurality of through holes are between adjacent pairs of the plurality of film wirings, a width of each of the plurality of through holes in the first direction decreases from the upper surface of the substrate to a lower surface of the substrate, and the under-fill layer is in each of the plurality of through holes. Claims 19-20 depend on claim 18.
Claims 9-10, 12-13, and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to REEMA PATEL whose telephone number is (571)270-1436. The examiner can normally be reached M-F, 8am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/REEMA PATEL/Primary Examiner, Art Unit 2812