DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 21 November 2023. The references cited on the PTOL 1449 form have been considered.
Specification
The disclosure is objected to because of the following informalities:
The written disclosure recites multiple instances (par. 5, 7, 31, 39, 42, 57, 66, 72, 82, 88, 120, 123, 127, 139, 141) of “poly silicon” and each should read -- polysilicon -- as one complete correctly spelled word without a space therebetween.
Appropriate correction is required.
Claim Objections
Claims 1-9, 13-17, 19 and 20 are objected to because of the following informalities:
Each of claims 1, 13 and 19 respectively recite “poly silicon” and should read -- polysilicon -- as one complete correctly spelled word without a space therebetween.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5 and 7-9 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Matsuura et al. (U.S. Patent Application Publication 2020/0083249).
Referring to Claim 1, Matsuura teaches in Fig. 15 or 20 for example, a semiconductor device, comprising: a substrate (20); a doped region (PP1 or PP2) on the substrate (20), the doped region (PP1 or PP2) including impurities of a first conductivity type at a first concentration (par. 86; p+) a gate structure (50-54, 60 and 61) on the substrate (20); and a first contact (CS) electrically connected to the doped region (PP1 or PP2), the first contact (CS) including a first portion (lower portion of 72; par. 119), a second portion (upper portion of 72) on the first portion (lower portion of 72), and a third portion (70, 71) on the second portion (upper portion of 72), the first portion (lower portion of 72) and the second portion (upper portion of 72) including poly silicon (par. 125), the third portion (70, 71) including at least one metallic material (par. 107), and the second portion (upper portion of 72) including impurities of the first conductivity type at a second concentration higher than the first concentration (par. 125-126, 147-158).
Referring to Claim 2, Matsuura further teaches an epitaxial pattern (EP) between the first contact (CS) and the doped region (PP1 or PP2), the first portion (lower portion of 72) of the first contact (CS) being in contact with a top surface of the epitaxial pattern (EP).
Referring to Claim 5, Matsuura further teaches wherein the epitaxial pattern (EP) includes a single crystalline silicon and impurities of the first conductivity type at a third concentration, the third concentration being lower than the second concentration (par. 120, 121, and 154).
Referring to Claim 7, Matsuura further teaches wherein the gate structure includes: a gate insulating layer (50, 51; par. 112-114); a first gate conductive layer (52; par. 114) on the gate insulating layer (50, 51); a second gate conductive layer (53; par. 115) on the first gate conductive layer (52), a level of a top surface of the second portion (upper portion of 72) of the first contact (CS) being higher than a level of a top surface of the second gate conductive layer (53); and a gate spacer (60, 61) on side surfaces of the gate insulating layer (50, 51), the first gate conductive layer (52), and the second gate conductive layer (53).
Referring to Claim 8, Matsuura further teaches a second contact (C0) in contact with the second gate conductive layer (53), the second contact (C0) including at least one metallic material (par. 107).
Referring to Claim 9, Matsuura further teaches an insulating structure (54, 62 and 63) covering the gate structure (50-53, 60 and 61), the insulating structure (54, 62 and 63) being in contact with the top surface of the second gate conductive layer (53).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 4, 10, 11 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuura et al. (U.S. Patent Application Publication 2020/0083249) in view of Czornomaz et al. (U.S. Patent Application Publication 2018/0294193) or Mazzocchi et al. (U.S. Patent Application Publication 2018/0261697).
Referring to Claims 3 and 4, Matsuura teaches the limitations of claim 2 but does not explicitly teach wherein the epitaxial pattern (EP) includes a first inclined surface, a second inclined surface, the top surface between the first inclined surface and the second inclined surface, the first side surface (right side portion of EP over PP1) connected to the first inclined surface, and the second side surface connected to the second inclined surface; and the first side surface (right side portion of EP over PP1) of the epitaxial pattern (EP) being in contact with a side surface of the gate structure (50-53, 60 and 61).
Czornomaz teaches in Fig. 1-8 for example (par. 37-54), an epitaxial pattern (RSD; 120 for example) on the substrate (104); the epitaxial pattern (RSD; 120) including a first inclined surface (upper right portion of 120), a second inclined surface (upper left portion of 120), a top surface (top portion of 120) between the first inclined surface (upper right portion of 120) and the second inclined surface (upper left portion of 120), a first side surface (right side portion of 120) connected to the first inclined surface (upper right portion of 120), and a second side surface (left side portion of 120) connected to the second inclined surface (upper left portion of 120); and the first side surface (right side portion of 120) of the epitaxial pattern (RSD; 120) being in contact with a side surface of the gate structure (110; 113-116).
Mazzocchi teaches in Fig. 3 and 5 for example, an epitaxial pattern (230b) on the substrate (203); the epitaxial pattern (230a) including a first inclined surface (upper right portion of 232b), a second inclined surface (upper left portion of 232b), a top surface (top portion of 232b) between the first inclined surface (upper right portion of 232b) and the second inclined surface (upper left portion of 232b), a first side surface (right side portion of 231b) connected to the first inclined surface (upper right portion of 232b), and a second side surface (left side portion of 231b) connected to the second inclined surface (upper left portion of 232b); and the first side surface (right side portion of 231b) of the epitaxial pattern (230b) being in contact with a side surface of the gate structure 210; 211, 213, 215).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the structure of the epitaxial pattern taught by Czornomaz or Mazzocchi for that of Matsuura based on its well-known suitability in the art for raised source/drains of transistors in order to provide low series resistance (Czornomaz; par. 3, 41-42), reduce stray capacitance (Mazzocchi; par. 6, 7 and 15) and a provide an overall reduced device footprint.
Referring to Claim 10, Matsuura teaches in Fig. for example a semiconductor device, comprising: a substrate (20); a doped region (PP1 or PP2) on the substrate (20); a gate structure (50-53, 60 and 61) on the substrate (20); an epitaxial pattern (EP) on the doped region (PP1 or PP2), the epitaxial pattern (EP) including a top surface, a first side surface (right side portion of EP over PP1), and a second side surface (left side portion of EP over PP1); and a contact (CS) on the epitaxial pattern (EP).
Matsuura does not explicitly teach wherein the epitaxial pattern (EP) includes a first inclined surface, a second inclined surface, the top surface between the first inclined surface and the second inclined surface, the first side surface (right side portion of EP over PP1) connected to the first inclined surface, and the second side surface connected to the second inclined surface; and the first side surface (right side portion of EP over PP1) of the epitaxial pattern (EP) being in contact with a side surface of the gate structure (50-53, 60 and 61).
Czornomaz teaches in Fig. 1-8 for example (par. 37-54), an epitaxial pattern (RSD; 120 for example) on the substrate (104); the epitaxial pattern (RSD; 120) including a first inclined surface (upper right portion of 120), a second inclined surface (upper left portion of 120), a top surface (top portion of 120) between the first inclined surface (upper right portion of 120) and the second inclined surface (upper left portion of 120), a first side surface (right side portion of 120) connected to the first inclined surface (upper right portion of 120), and a second side surface (left side portion of 120) connected to the second inclined surface (upper left portion of 120); and the first side surface (right side portion of 120) of the epitaxial pattern (RSD; 120) being in contact with a side surface of the gate structure (110; 113-116).
Mazzocchi teaches in Fig. 3 and 5 for example, an epitaxial pattern (230b) on the substrate (203); the epitaxial pattern (230a) including a first inclined surface (upper right portion of 232b), a second inclined surface (upper left portion of 232b), a top surface (top portion of 232b) between the first inclined surface (upper right portion of 232b) and the second inclined surface (upper left portion of 232b), a first side surface (right side portion of 231b) connected to the first inclined surface (upper right portion of 232b), and a second side surface (left side portion of 231b) connected to the second inclined surface (upper left portion of 232b); and the first side surface (right side portion of 231b) of the epitaxial pattern (230b) being in contact with a side surface of the gate structure 210; 211, 213, 215).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the structure of the epitaxial pattern taught by Czornomaz or Mazzocchi for that of Matsuura based on its well-known suitability in the art for raised source/drains of transistors in order to provide low series resistance (Czornomaz; par. 3, 41-42), reduce stray capacitance (Mazzocchi; par. 6, 7 and 15) and a provide an overall reduced device footprint.
Referring to Claim 11, as modified above, Czornomaz and Mazzocchi, respectively, further teach wherein the first side surface (right surface portion) and the second side surface (left surface portion) of the epitaxial pattern are parallel to the side surface of the gate structure.
Referring to Claim 13, as modified above, Matsuura further teaches wherein: the contact includes a first portion (lower portion of 72) on the epitaxial pattern (EP), a second portion (upper portion of 72) on the first portion (lower portion of 72), and a third portion (70, 71) on the second portion (upper portion of 72), the first portion (lower portion of 72) and the second portion (upper portion of 72) of the contact include poly silicon (par. 125), and the third portion (70, 71) of the contact includes at least one metallic material (par. 107).
Referring to Claim 14, as modified above, Matsuura further teaches the semiconductor device as wherein: the epitaxial pattern (EP) includes impurities of a first conductivity type at a first concentration, the second portion (upper portion of 72) of the contact includes impurities of the first conductivity type at a second concentration, and the first concentration is lower than the second concentration (par. 120, 121, and 154).
Referring to Claim 15, as modified above, Matsuura further teaches wherein the first portion (lower portion of 72) of the contact (CS) includes impurities of the first conductivity type at a third concentration, the third concentration being lower than the second concentration (par. 125-126, 147-158).
Referring to Claim 16, as modified above, Matsuura further teaches wherein the third portion (70, 71) of the contact (CS) includes a barrier layer (71) on the second portion (upper portion of 72) and a conductive layer (70) on the barrier layer (71).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuura et al. (U.S. Patent Application Publication 2020/0083249) in view of Czornomaz et al. (U.S. Patent Application Publication 2018/0294193) or Mazzocchi et al. (U.S. Patent Application Publication 2018/0261697) in further view of Baars (U.S. Patent Application Publication 2019/0043963) or Chen (U.S. Patent Application Publication 2015/0206945) or Smith et al. (U.S. Patent Application Publication 2017/0345914).
Referring to Claim 18, Matsuura in view of Czornomaz or Mazzocchi teach the limitations of claim 10 but do not explicitly show wherein a width of the contact is smaller than a width of the epitaxial pattern.
In the same field of endeavor, Baars teaches in Fig. 8A and 10, wherein a width of the contact (in openings 108) is smaller than a width of the epitaxial pattern (151) (par. 65).
In the same field of endeavor, Chen teaches in Fig. 3I, wherein a width of the contact (80) is smaller than a width of the epitaxial pattern (35) (par. 24-25).
In the same field of endeavor, Smith teaches in Fig. 7A and 7B, wherein a width of the contact (704-707) is smaller than a width of the epitaxial pattern (602-605) (par. 68).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to provide a contact having a width smaller as taught by Baars or Chen or Smith than that of the epitaxial pattern of Matsuura in view of Czornomaz or Mazzocchi to reduce leakage currents and control any capacitive effects with respect to the gate.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gasner (U.S. Patent 4,223,334) in view of Matsuura et al. (U.S. Patent Application Publication 2020/0083249).
Referring to Claim 19, Gasner teaches in Fig. 6 for example, a semiconductor device, comprising: a substrate (10); an isolation region (28) on the substrate (10), the isolation region (28) including impurities (n-type); a device isolation layer (30) on the isolation region (28) between CMOS transistors (36 and 40); a doped region (38) on the substrate (10), the doped region (38) including impurities (p-type) of a first conductivity type, the impurities of the doped region (38) being of a different conductivity than the impurities (n-type) of the isolation region (28); a gate structure (polysilicon and gate oxide; Col. 4, Lines 12-21) on the substrate (10); an insulating structure (final oxide; Col. 4, lines 21-23) covering the gate structure (polysilicon and gate oxide; Col. 4, Lines 12-21); and a contact (metal contact; Col. 4, Lines 12-21) electrically connected to the doped region (38), the contact including a first portion (lower portion), a second portion (middle portion) on the first portion (lower portion), and a third portion (upper portion) on the second portion (middle portion), the third portion (upper portion) including at least one metallic material.
Gasner does not explicitly teach wherein the first portion (lower portion) and the second portion (middle portion) include poly silicon, and the second portion (middle portion) includes impurities of the first conductivity type.
Matsuura teaches in Fig. 15 or 20 for example, a semiconductor device, comprising: a substrate (20); an device isolation layer (STI; Fig. 4) of the substrate (20) between CMOS transistors (TrN and TrP); a doped region (PP1 or PP2) on the substrate (20), the doped region (PP1 or PP2) including impurities of a first conductivity type (par. 86; p+); a gate structure (50-54, 60 and 61) on the substrate (20); an insulating structure (54, 62 and 63) covering the gate structure (50-54, 60 and 61); and a contact (CS) electrically connected to the doped region (PP1 or PP2), the contact (CS) including a first portion (lower portion of 72; par. 119), a second portion (upper portion of 72) on the first portion (lower portion of 72), and a third portion (70, 71) on the second portion (upper portion of 72), the first portion (lower portion of 72) and the second portion (upper portion of 72) including poly silicon (par. 125), the third portion (70, 71) including at least one metallic material (par. 107), and the second portion (upper portion of 72) including impurities of the first conductivity type (par. 125-126, 147-158).
Therefore it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the contact structure of Matsuura for that of Gasner in order to suppress an increase in contact resistance and a variation in characteristics of the transistors (par. 155-158 and186).
In an alternative modification, it would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the isolation region of Gasner under the device isolation layer of Matsuura in order to improve device isolation between the CMOS transistors (Col. 1, Lines 55-59; Col. 2, Lines 36-50; Col. 4, Lines 24-39).
Referring to Claim 20, as modified above, Matsuura further teaches wherein a level of a top surface of the second portion (upper portion of 72) of the contact (CS) is higher than a level of a top surface of the gate structure (50-54, 60 and 61).
Allowable Subject Matter
Claims 6, 12 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 6, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein the first portion of the first contact does not contain an impurity in combination with all of the limitations of Claim 1 and 6.
Regarding Claim 12, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein the top surface of the epitaxial pattern is at a level lower than a top surface of the first gate conductive layer in combination with all of the limitations of Claim 10 and 12.
Regarding Claim 17, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein a level of a bottom surface of the first portion of the contact is lower than a level of a top surface of the doped region in combination with all of the limitations of Claims 10, 13 and 17.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
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