DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The previous indication of allowability with respect to claim 17 required all the limitations of previous claims 10 and 13. Currently presented claim 17 does not include all those limitations.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shioda et al. (U.S. Patent Application Publication 2022/0077286) cited on applicant’s IDS dated 21 March 2023.
Referring to Claim 17, Shioda teaches in Fig. 5 or 7 for example, a semiconductor device, comprising: a substrate (10); a doped region (20 or 21) on the substrate (10); a gate structure (30/40/42/80) on the substrate; and a contact (52/50/70) on the doped region (20 or 21); a level of a bottom surface of a first portion (52) of the contact (52/50/70) is higher than a level of a bottom surface of the doped region (20 or 21) and is lower than a level of a top surface of the doped region (20 or 21). It is noted that Shioda also teaches other embodiments having a contact (50/70) of Fig. 3-4, 6 and 17, that also teach the claim limitations.
Allowable Subject Matter
Claims 1-11,13-16 and 18-20 are allowable.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 1, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device, comprising: the first contact including a first portion, a second portion on the first portion, and a third portion on the second portion, the first portion and the second portion including polysilicon, the third portion including at least one metallic material, and the second portion including impurities of the first conductivity type at a second concentration higher than the first concentration; wherein: a vertical length of the first portion is larger than a vertical length of the second portion; and the second concentration of the second portion is higher than a concentration of impurities in the first portion in combination with all of the limitations of Claim 1. Claims 2-9 include the limitations of claim 1.
Regarding Claim 6, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device, comprising: the first contact including a first portion, a second portion on the first portion, and a third portion on the second portion, the first portion and the second portion including polysilicon, the third portion including at least one metallic material, and the second portion including impurities of the first conductivity type at a second concentration higher than the first concentration; wherein the first portion of the first contact does not contain an impurity in combination with all of the limitations of Claim 6.
Regarding Claim 10, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device, comprising: wherein the gate structure includes: a first gate conductive layer on the gate insulating layer; a second gate conductive layer on the first gate conductive layer; and a gate spacer on side surfaces of the gate insulating layer, the first gate conductive layer, and the second gate conductive layer, wherein the top surface of the epitaxial pattern is at a level higher than a top surface of the gate insulating layer and lower than a top surface of the first gate conductive layer in combination with all of the limitations of Claim 10. Claims 11, 13-16 and 18 include the limitations of claim 10.
Regarding Claim 19, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device, comprising: the contact including a first portion, a second portion on the first portion, and a third portion on the second portion, the first portion and the second portion including polysilicon, polysilicon, the third portion including at least one metallic material, and the second portion including impurities of the first conductivity type; wherein a vertical length of the first portion is lamer than a vertical length of the second portion; and a concentration of the impurities in the second portion is higher than a concentration of impurities in the first portion in combination with all of the limitations of Claim 19. Claim 20 includes the limitations of claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
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