DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR DEVICES WITH ETCH STOP LAYER
Election/Restrictions
Applicant's election with traverse of n the reply filed on 5/18/2026 is acknowledged. The traversal is is persuasive and the restriction requirement is withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-12 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Sasaki (US 20200365509), hereinafter Sasaki.
Regarding claim 1, Sasaki (US 20200365509) (see Figures 1, 2A-2C and 3) teaches a semiconductor device comprising:
a substrate (SL, described as "semiconductor layer SL may have a first surface SLa and a second surface SLb" in para 17);
an active region (FN1 and/or FN2, described as "first active patterns FN1" and " second active patterns FN2 " in para 22; best seen in Figure 2B) extending on the substrate in a first direction (D3 direction – best seen in Figure 2B);
a protective layer (LIL1, see para 44) on a lower (see 35 USC, 112, 2nd paragraph rejection above) surface of the substrate;
an etch stop layer (formed by “an etch stop dopant ESD” – see para 49 and Figure 3) on a lower surface of the protective layer;
a device isolation layer (ST, described as "device isolation layer ST" in para 18; see Figure 3) defining the active region;
a gate structure (comprising GE, described as " Gate electrodes GE" in para 30) on the active region and extending in a second direction (D2 direction – best seen in Figure 2A; note that any 3D structure extends in all directions in space) intersecting the first direction (D3);
a source/drain region (SD1 and/or SD2, described as "upper portion of each of the first active patterns FN1 may include first channel regions CH1 and/or first source/drain regions SD1" and "upper portion of each of the second active patterns FN2 may include second channel regions CH2 and/or second source/drain regions SD2" in para 26) on the active region (FN1 and/or FN2) on both lateral (see 35 USC, 112, 2nd paragraph rejection above) sides of the gate structure (GE);
a contact structure (AC – best seen in Figure 3, described as "Active contacts AC may penetrate the first and second upper insulating layers UIL1 and UIL2 between a pair of the gate electrodes GE so as to be electrically connected to the first and/or second source/drain regions SD1 and SD2." in para 35) connected to the source/drain region; and
a power transmission structure (PON – best seen in Figure 3, described as "power delivery network PON may be provided on the second surface SLb of the semiconductor layer SL" in para 44) electrically connected to the contact structure (PON is connected to AC by way of TV1 & POR1 as well as TV2 & POR2 – best seen in Figure 2B; also see para 21).
Regarding claim 5, Sasaki (refer to Figures 1, 2A-2C and 3) teaches the semiconductor device of claim 1, wherein the etch stop layer formed by “an etch stop dopant ESD” in a surface of SL such as SLb – see para 49 and Figure 3) includes at least one of silicon (Si) or silicon germanium (SiGe) {because para 17 describes "semiconductor layer SL may include silicon, germanium, or a combination thereof"} and at least one of a group 13 element or a group 15 element of the periodic table of elements (e.g. because SL surface is doped with B, as described in para 49, and B; i.e. boron, belongs to group 13 of the periodic table).
Regarding claim 6, Sasaki (refer to Figures 1, 2A-2C and 3) teaches the semiconductor device of claim 1, further comprising a buried conductive structure (POR1 and/or POR2, described as "first and/or second power rails POR1 and POR2 may be buried in the device isolation layer ST" in para 20) connected to (best seen in Figure 2B, also see para 21) the contact structure (AC) and passing through the device isolation layer (ST), wherein the power transmission structure (PON) passes through the protective layer (LIL1) and the etch stop layer (formed by “an etch stop dopant ESD”).
Regarding claim 7, Sasaki (refer to Figures 1, 2A-2C and 3) teaches the semiconductor device of claim 1, further comprising a lower interlayer insulating layer on a lower surface of the etch stop layer (para 49).
Regarding claim 8, Sasaki (refer to Figures 1, 2A-2C and 3) teaches the semiconductor device of claim 7, wherein the etch stop layer is between the protective layer and the lower interlayer insulating layer (para 49).
Regarding claim 9, Sasaki (refer to Figures 1, 2A-2C and 3) teaches the semiconductor device of claim 8, wherein the power transmission structure passes through the lower interlayer insulating layer (para 52).
Regarding claim 10, Sasaki (refer to Figures 1, 2A-2C and 3) teaches the semiconductor device of claim 1, wherein the active region comprises a base active region (base part of FN1 and/or FN2 thatis adjacent SLa) and at least one active fin (remainder part of FN1 and/or FN2 adjacent SD1 and/or SD2), wherein the at least one active fin protrudes from the base active region and extends in the first direction (i.e. D3 – best seen in Figure 2B).
Regarding claim 11, Sasaki (refer to Figures 1, 2A-2C and 3) teaches the semiconductor device of claim 10, further comprising a plurality of channel layers (CH1 and/or CH2, described as "first channel regions CH1" and "second channel regions CH2" in para 26 – best seen in Figure 2C) that are spaced apart in a third direction (i.e. D1 – best seen in Figure 2C) substantially perpendicular to a major surface of the substrate from one another and at least one active fin and surrounded by the gate structure.
Regarding claim 12, Sasaki (refer to Figures 1, 2A-2C and 3) teaches the Semiconductor device of claim 11, wherein at least a portion of the plurality of channel layers comprise at least one of a carbon (C) element or an oxygen (O) element, wherein a concentration of the at least one carbon (C) element or oxygen (O) element decreases toward an upper portion in the plurality of channel layers (para 26).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki.
Regarding claim 2, Sasaki (refer to Figures 1, 2A-2C and 3) teaches the semiconductor device of claim 1, wherein the protective layer (LIL1) is an insulating layer (para 44) and that it is formed on the second surface (SLb) of the silicon substrate (SL, see para 78) and para 17 describes "semiconductor layer SL may include silicon, germanium, or a combination thereof", but does not teach that the insulating material of the protective layer comprises at least one of “silicon (Si) or silicon germanium (SiGe), and at least one of a carbon (C) element or an oxygen (O) element”. However, Sasaki teaches dielectric materials may be silicon oxide or when high-k dielectric is required, hafnium-silicon oxide is known insulating material (para 32). It would have been obvious to one of ordinary skills in the art before the effective filing of the claimed invention to modify Sasaki so that the protective layer (LIL1) is formed by a known technique for forming insulating layers; i.e. oxidation of semiconductor layer; i.e. material comprises at least oxygen and material of SL; i.e. at least silicon, germanium, or a combination thereof, such as SiGe. The ordinary artisan would have been motivated to modify Sasaki for at least the purpose of forming the insulating material of the protective layer by a known process of oxidation of the substrate semiconductor layer.
Regarding claim 3, Sasaki (refer to Figures 1, 2A-2C and 3) teaches the semiconductor device of claim 1, wherein the etch stop layer comprises impurities (i.e. dopant, see para 49, especially 1st two sentences) in a concentration ranging from (para 49 describes range of 1E16/ cm3 to 5E21/cm3 (para 49, especially 2nd last sentence; also see dopant profile in Figure 3), which overlaps with the claimed range of “from about 1×1019 atoms/cm3 or higher to about 1×1022 atoms/cm3 “. Overlapping ranges
Regarding claim 4, Sasaki (refer to Figures 1, 2A-2C and 3) teaches the semiconductor device of claim 3, wherein the impurities comprise at least boron (B) {i.e. dopant is at least B, see para 49, especially 1st two sentences}.
Claims 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki. in view of Ontalus (US 20180108654), hereinafter Ontalus.
Regarding claim 13, Sasaki (US 20200365509) (see Figures 1, 2A-2C and 3) teaches a semiconductor device comprising:
a substrate (SL, described as "semiconductor layer SL may have a first surface SLa and a second surface SLb" in para 17);
an active region (FN1 and/or FN2, described as "first active patterns FN1" and " second active patterns FN2 " in para 22; best seen in Figure 2B) extending on the substrate in a first direction (D3 direction – best seen in Figure 2B);
a plurality of channel layers (CH1 and/or CH2, described as "first channel regions CH1" and "second channel regions CH2" in para 26 – best seen in Figure 2C) on the active region (FN1 and/or FN2) spaced apart from each other in a direction perpendicular to an upper surface of the substrate;
a device isolation layer (ST, described as "device isolation layer ST" in para 18; see Figure 3) defining the active region (FN1 and/or FN2);
a gate structure (comprising GE, described as " Gate electrodes GE" in para 30) on the active region and extending in a second direction (D2 direction – best seen in Figure 2A; note that any 3D structure extends in all directions in space) intersecting the first direction (D3);
a source/drain region (SD1 and/or SD2, described as "upper portion of each of the first active patterns FN1 may include first channel regions CH1 and/or first source/drain regions SD1" and "upper portion of each of the second active patterns FN2 may include second channel regions CH2 and/or second source/drain regions SD2" in para 26) on the active region (FN1 and/or FN2) on both lateral (see 35 USC, 112, 2nd paragraph rejection above) sides of the gate structure (GE);
a contact structure (AC – best seen in Figure 3, described as "Active contacts AC may penetrate the first and second upper insulating layers UIL1 and UIL2 between a pair of the gate electrodes GE so as to be electrically connected to the first and/or second source/drain regions SD1 and SD2." in para 35) connected to the source/drain region;
a buried conductive structure (POR1 and/or POR2, described as "first and/or second power rails POR1 and POR2 may be buried in the device isolation layer ST" in para 20) connected to (best seen in Figure 2B, also see para 21) the contact structure (AC);
a lower interlayer insulating layer (LIL2, para 45) on a lower surface of the substrate; and
a power transmission structure (comprising LML1 and LML2 – see para 44) passing through the lower interlayer insulating layer (LIL2) and connected to the buried conductive structure
a power transmission structure passing through the lower interlayer insulating layer and connected to (by TV1, see para 21 and Figure 3) the buried conductive structure (POR1 and/or POR2).
Sasaki does not teach wherein at least a portion of the active region and the plurality of channel layers includes “a group 13 element or a group 15 element of the periodic table of elements in a first concentration”, and at least a portion of “the active region and the plurality of channel layers includes at least one of a carbon (C) element or an oxygen (O) element in a second concentration”.
Ontalus (US 20180108654) teaches that in fin-type devices, active region and channel region may include carbon element (para 61 describes "a dopant diffusion-inhibiting species such as carbon". Ontalus further describes that the concentration of carbon can vary with location within the channel region and active region (see para 63 and Figure 7), with the target of achieving ability to form an abrupt junction that in turn enables a greater overall dopant concentration within the fins while mitigating dopant punch through and a concomitant degradation of short channel effects (para 63). Thus, concentration of the carbon (C) element in the active region is a known results effective variable, and it’s relationship to achieving a target abrupt junction (described above) is also known, while carbon in protective layer is to provide etch stop function. Optimization. Motivation: at least for the purpose of employing a concentration of carbon in the protective layer to provide required etch stop property while the concentration profile of carbon in active region is tailored to mitigate dopant punch through and a concomitant degradation of short channel effects (para 63 of Ontalus)
Regarding claim 20, Sasaki (US 20200365509) (see Figures 1, 2A-2C and 3) teaches a semiconductor device comprising:
a substrate (SL, described as "semiconductor layer SL may have a first surface SLa and a second surface SLb" in para 17);
an active region (FN1 and/or FN2, described as "first active patterns FN1" and " second active patterns FN2 " in para 22; best seen in Figure 2B) extending on the substrate in a first direction (D3 direction – best seen in Figure 2B);
a protective layer (formed by layer with “an etch stop dopant ESD” on lower surface of the substrate– see para 49 and Figure 3) on a lower surface of the substrate, including at least one of silicon (Si) or silicon germanium (SiGe) {because para 17 describes "semiconductor layer SL may include silicon, germanium, or a combination thereof"}, and at least one of a carbon (C) element or an oxygen (O) element {para 49 describes "etch stop dopant ESD may include boron (B), carbon (C), or a combination thereof"}
a device isolation layer (ST, described as "device isolation layer ST" in para 18; see Figure 3) defining the active region (FN1 and/or FN2);
a gate structure (comprising GE, described as " Gate electrodes GE" in para 30) on the active region and extending in a second direction (D2 direction – best seen in Figure 2A; note that any 3D structure extends in all directions in space) intersecting the first direction (D3);
a source/drain region (SD1 and/or SD2, described as "upper portion of each of the first active patterns FN1 may include first channel regions CH1 and/or first source/drain regions SD1" and "upper portion of each of the second active patterns FN2 may include second channel regions CH2 and/or second source/drain regions SD2" in para 26) on the active region (FN1 and/or FN2) on both lateral (see 35 USC, 112, 2nd paragraph rejection above) sides of the gate structure (GE);
a contact structure (AC – best seen in Figure 3, described as "Active contacts AC may penetrate the first and second upper insulating layers UIL1 and UIL2 between a pair of the gate electrodes GE so as to be electrically connected to the first and/or second source/drain regions SD1 and SD2." in para 35) connected to the source/drain region; and
a power transmission structure (PON – best seen in Figure 3, described as "power delivery network PON may be provided on the second surface SLb of the semiconductor layer SL" in para 44) electrically connected to the contact structure (PON is connected to AC by way of TV1 & POR1 as well as TV2 & POR2 – best seen in Figure 2B; also see para 21).
Sasaki does not teach that wherein the active region includes “at least one of the carbon (C) element or the oxygen (O) element, and a concentration of the carbon (C) element or a concentration of the oxygen (O) element in the protective layer is higher than a concentration of the carbon (C) element or the oxygen (O) element in the active region”.
Ontalus (US 20180108654) teaches that in fin-type devices, active region and channel region may include carbon element (para 61 describes "a dopant diffusion-inhibiting species such as carbon". Ontalus further describes that the concentration of carbon can vary with location within the channel region and active region (see para 63 and Figure 7), with the target of achieving ability to form an abrupt junction that in turn enables a greater overall dopant concentration within the fins while mitigating dopant punch through and a concomitant degradation of short channel effects (para 63). Thus, concentration of the carbon (C) element in the active region is a known results effective variable, and it’s relationship to achieving a target abrupt junction (described above) is also known, while carbon in protective layer is to provide etch stop function. Optimization. Motivation: at least for the purpose of employing a concentration of carbon in the protective layer to provide required etch stop property while the concentration profile of carbon in active region is tailored to mitigate dopant punch through and a concomitant degradation of short channel effects (para 63 of Ontalus)
Conclusion
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/AJAY ARORA/Primary Examiner, Art Unit 2892
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