Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 07/06/2026 is acknowledged.
Claims 11-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/06/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7, and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US9514988B1, hereinafter Lin).
Regarding claim 1, Lin discloses a packaging structure, comprising:
a substrate, comprising a bonding surface (Fig. 2 support 150 comprises film 160 which is bonded to and supports wafer 400);
a device chip, comprising a first side and a second side opposite to the first side (Fig. 2 rightmost IC die 135 has first side bottom and second side up), the first side being bonded to the bonding surface and electrically connected to the substrate (Fig. 2 bottom side of rightmost IC die 135 bonded to frontside redistribution layer, FSRDL, 140 which is bonded and electrically connected to film 160);
a conductive pillar, bonded to the bonding surface at a side of the device chip and electrically connected to the substrate (Fig. 2 vias 132 bonded to FSRDL 140 at a side of rightmost IC die 135 and electrically connected to film 160); and
a first redistribution structure, located on the second side of the device chip and a side of the conductive pillar facing away from the bonding surface, the first redistribution structure being electrically connected to the second side of the device chip and the conductive pillar (Fig. 2 backside redistribution layer, BSRDL, 120 located on and electrically connected to top side of rightmost IC die 135 and vias 132).
Regarding claim 2, Lin discloses the packaging structure according to claim 1,
wherein the first side is a front side of the device chip, and the second side is a back side of the device chip (Fig. 2 rightmost IC die 135 has first side bottom and second side up. The bottom side is connected to FSRDL 140 and the top side is connected to BSRDL 120).
Regarding claim 3, Lin discloses the packaging structure according to claim 1,
wherein the packaging structure further comprises:
a packaging layer, located on the first redistribution structure and covering the device chip and side walls of the conductive pillar (Fig. 2 molding compound 130 formed on FSRDL 140 and covering rightmost IC chip 135 and vias 132).
Regarding claim 7, Lin discloses the packaging structure according to claim 1, wherein the packaging structure further comprises:
a second redistribution structure, located on the first side of the device chip and a side of the conductive pillar facing the substrate, the second redistribution structure being electrically connected to the device chip and the conductive pillar (Fig. 2 FSRDL 140 located on and electrically connected to bottom side of rightmost IC die 135 and vias 132).
Regarding claim 9, Lin discloses the packaging structure according to claim 1, wherein the packaging structure further comprises:
a third conductive bump, located on a surface of the substrate facing away from the bonding surface, the third conductive bump being for enabling electrical connection between the packaging structure and an external circuit (Fig. 2 external connectors 148 located on surface of FSRDL 140 away from rightmost IC die 135 and external connectors 148 enable electrical connections with external circuits).
Regarding claim 10, Lin discloses the packaging structure according to claim 7,
wherein the first redistribution structure comprises one or more first redistribution layers (Fig. 2 illustrates BSRDL 120 comprising a plurality of interconnection layers), and
the second redistribution structure comprises one or more second redistribution layers (Fig. 2 illustrates FSRDL 140 comprising a plurality of interconnection layers).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Tao (US20030030134A1).
Regarding claim 4, Lin teaches the packaging structure according to claim 1.
Lin does not appear to teach
wherein the packaging structure further comprises:
first conductive bumps, located between the device chip and the first redistribution structure and electrically connecting the device chip to the first redistribution structure.
Tao teaches
wherein the packaging structure further comprises:
first conductive bumps, located between the device chip and the first redistribution structure and electrically connecting the device chip to the first redistribution structure (Fig. 1 solder bumps 6 located between semiconductor chip 5 and RDL structure within substrate 1).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Tao because, as both Lin and Tao teach suitable methods for bonding a semiconductor structure to a redistribution structure, it would have been obvious to substitute Lin’s direct bonding with Tao’s solder bump binding to achieve the predictable result of bonding Lin’s rightmost IC die 135 to BSRDL 120 with solder bump binding.
Regarding claim 5, the combination of Lin and Tao teaches the packaging structure according to claim 4.
Tao further teaches wherein the packaging structure further comprises:
a first sealing layer, filled in a gap between adjacent first conductive bumps and covering the first conductive bumps (Fig. 1 underfill resin 7 disposed between solder bumps 6).
Being in analogous arts it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lin and Tao with additional teachings from Tao because “it is possible to relax the thermal stress generated between the semiconductor chip 5 and the package substrate 1, and prevent the warp of the semiconductor chip 5 and the package substrate 1 directly below the chip 5” by the use of underfill resin between solder bumps and so a person of ordinary skill would be motivated to disposed the resin between the solder bumps that bind Lin’s rightmost IC die 135 to BSRDL 120 as taught in above claim 4 (Tao par. 34).
Regarding claim 6, Lin teaches the packaging structure according to claim 1
Lin does not appear to teach wherein the packaging structure further comprises:
second conductive bumps, located between the device chip and the substrate and between the conductive pillar and the substrate, electrically connecting the device chip to the substrate and electrically connecting the conductive pillar to the substrate.
Tao teaches
second conductive bumps, located between the device chip and the substrate and between the conductive pillar and the substrate, electrically connecting the device chip to the substrate and electrically connecting the conductive pillar to the substrate (Fig. 1 solder bumps 6 located between semiconductor chip 5 and RDL structure within substrate 1).
Being in analogous arts, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin with the teachings of Tao because, as both Lin and Tao teach suitable methods for bonding a semiconductor structure to a redistribution structure, it would have been obvious to substitute Lin’s direct bonding with Tao’s solder bump binding to achieve the predictable result of bonding Lin’s rightmost IC die 135 and vias 132 to FSRDL 140 with solder bump binding.
Regarding claim 8, the combination of Lin and Tao teaches the packaging structure according to claim 6.
Tao additionally teaches wherein the packaging structure further comprises:
a second sealing layer, filled in a gap between adjacent second conductive bumps and covering the second conductive bumps (Fig. 1 underfill resin 7 disposed between solder bumps 6).
Being in analogous arts it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the combination of Lin and Tao with additional teachings from Tao because “it is possible to relax the thermal stress generated between the semiconductor chip 5 and the package substrate 1, and prevent the warp of the semiconductor chip 5 and the package substrate 1 directly below the chip 5” by the use of underfill resin between solder bumps and so a person of ordinary skill would be motivated to disposed the resin between the solder bumps that bind Lin’s rightmost IC die 135 and vias 132 to FSRDL 140 as taught in above claim 6 (Tao par. 34).
Conclusion
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/COLE LEON LINDSEY/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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