DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending in this application. Acknowledgement is made of the amendment received 3/12/26 withdrawing claims 13-20.
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-12) in the reply filed on 3/12/26 is acknowledged. Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected inventions, there being no allowable generic or linking claim. Claims 1-12 are examined in this Office action.
Foreign Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
An information disclosure statement has not been received. If the applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same.
Drawings
There are no objections or rejections to the drawings.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7 and 10-12 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Agarwal et al. (US Patent Application Publication No 2022/0208712) hereinafter referred to as Agarwal.
Per Claim 1 Agarwal discloses a packaging structure device, comprising (see figure 6)
a substrate (34), comprising a bonding surface (as described in [0046]); (see figure 6)
a device chip (20), comprising a first (bottom) side and a second (top) side opposite to the first side, (see figure 6) the first side of the device chip being bonded to the bonding surface and electrically connected to the substrate (described in [0046]), and the second side of the device chip comprising a first chip area (left side) and a second chip area (right side) adjacent to the first chip area; The examiner notes that the term "connected" includes "directly connected" (no intermediate materials, elements or space disposed therebetween) and "indirectly connected " (intermediate materials, elements or space disposed therebetween). The examiner notes that the term "electrically connected" includes both ohmic (metallic) connection as well as capacitive (insulating) connection.
a first interconnect chip (18), bonded to the bonding surface at a side portion of the device chip and electrically connected to the substrate (as described in [0046]; see figure 6) and
a second interconnect chip (24), bonded to the first chip area (left) of the device chip (20) and the first interconnect chip (18) (as shown in figure 6), the second interconnect chip being electrically connected to the first interconnect chip and the device chip (described in [0047]), and the second interconnect chip exposing the second chip area. (see figure 6)
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Per Claim 2 Agarwal discloses the device of claim 1 including where the first (bottom) side is a front side of the device chip, and the second side is a back side of the device chip. (see figures 6).
Per Claim 3 Agarwal discloses the device of claim 1 including where the packaging structure further comprises: a first packaging layer (16), covering side walls of the device chip and the first interconnect chip. (as shown in figure 6)
Per Claim 7 Agarwal discloses the device of claim 1 including where a top surface of the first interconnect chip (18) is flush with the second (top) side of the device chip (20). (as shown in figure 6)
Per Claim 10 Agarwal discloses the device of claim 1 including where a first interconnection structure (44, shown in figure 4) running through the first interconnect chip (18) is formed in the first interconnect chip (18), and the substrate is electrically connected to the second interconnect chip (24) bonded to the first interconnect chip through the first interconnection structure. (as shown in figure 6)
Per Claim 11 Agarwal discloses the device of claim 1 including where a second interconnection structure (58is formed in the second interconnect chip (24), and the second interconnect chip is electrically connected to the device chip through the second interconnection structure. (as shown in figure 6)
Per Claim 12 Agarwal discloses the device of claim 1 including where the second interconnect chip (24) comprises a chip bridge or a chip comprising a plurality of re-distributed layers. [0048]
Allowable Subject Matter
Claims 4-6 and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached on Monday-Thursday 7am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jami Valentine Miller/Primary Examiner, Art Unit 2818
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