DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Species I directed to Figs. 5A-5C and 6A-6C (Claims 1-20) in the reply filed on March 5th, 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4, 7, 11, 14 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 4 recites limitation “an n to p ratio” in line 1. It is unclear to the examiner what are the parameters n and p for determining the n to p ratio.
Claim 7 recites limitation “an n to p ratio” in line 2. It is unclear to the examiner what are the parameters n and p for determining the n to p ratio.
Claim 11 recites limitation “an n to p ratio” in line 1. It is unclear to the examiner what are the parameters n and p for determining the n to p ratio.
Claim 14 recites limitations “a first n to p ratio” in line 2 and “a second n to p ratio” in line 3. It is unclear to the examiner what are the parameters n and p for determining the first and second n to p ratios.
Claim 20 recites limitations “a first n to p ratio” in line 2 and “a second n to p ratio” in line 3. It is unclear to the examiner what are the parameters n and p for determining the first and second n to p ratios.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 8-10, 12-13, and 15-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LIANG et al. (Pub. No.: US 2024/0105786 A1), hereinafter as LIANG.
Regarding claim 1, LIANG discloses a semiconductor structure in Figs. 7 and 13A-13C, comprising: a substrate (substrate 50) (see Fig. 8A and [0021], [0045]); one or more nanosheet channel layers (nanostructures 56B) disposed over the substrate (see Fig. 8A and [0028]); and a dielectric bar (dielectric wall 68) attached to the one or more nanosheet channel layers (see Figs. 8A-8B and [0036]); wherein the dielectric bar is not perpendicular to the substrate (dielectric wall 68 has tapered shape with the sidewall is not perpendicular to the surface of substrate 50) (see Fig. 13A-13B).
Regarding claim 2, LIANG discloses the semiconductor structure of claim 1, wherein the one or more nanosheet channel layers comprise a first set of one or more nanosheet channels (nanostructures 56B in region of fin structures 62N) attached to a first side of the dielectric bar (one side of dielectric wall 68) and a second set of one or more nanosheet channels (nanostructures 56B in region of fin structure 62P) attached to a second side of the dielectric bar (another side of dielectric wall 68) (see Fig. 7 and Figs. 13A-13B and [0028], [0056]).
Regarding claim 3, LIANG discloses the semiconductor structure of claim 2,
wherein the first set of one or more nanosheet channels comprise channels for n-type transistors (NFETs) and the second set of one or more nanosheet channels comprise channels for p-type transistors (PFETs) (see Figs. 6, 13A-13B and [0022], [0047]).
Regarding claim 5, LIANG discloses the semiconductor structure of claim 1, further comprising: one or more additional nanosheet channel layers (another nanostructure 56B) disposed over the substrate (see Figs. 7, 13A and [0028], [0045]); and an additional dielectric bar (another dielectric wall 68) attached to the one or more additional nanosheet channel layers (see Figs. 7, 13A and [0036], [0038], [0044]), the additional dielectric bar being perpendicular to the substrate (the other dielectric wall 68 has tapered shape with the sidewall is not perpendicular to the surface of substrate 50) (see Fig. 13A-13B).
Regarding claim 6, LIANG discloses the semiconductor structure of claim 5, wherein: the one or more nanosheet channel layers comprise a first set of one or more nanosheet channels (nanostructures 56B in region of one of fin structures 62N) attached to a first side of the dielectric bar (one side of dielectric wall 68) providing channels for a first set of n-type transistors (a group of NFETs of one of fin structures 62N) and a second set of one or more nanosheet channels (nanostructures 56B in region of one of fin structures 62P) attached to a second side of the dielectric bar (another side of dielectric wall 68) providing channels for a first set of p-type transistors (a group of PFETs one of fin structures 62P) (see Fig. 7 and Figs. 13A-13B and [0028], [0056]); and the one or more additional nanosheet channel layers comprise a third set of one or more nanosheet channels (nanostructures 56B in region of another one of fin structures 62N) attached to a first side of the additional dielectric bar (one side of another dielectric wall 68) providing channels for a second set of n-type transistors (a group of NFETs of another one of fin structures 62N) and a fourth set of one or more nanosheet channels (nanostructures 56B in region of another one of fin structures 62P) attached to a second side of the additional dielectric bar (another side of the other dielectric wall 68) providing channels for a second set of p-type transistors (a group of PFETs another one of fin structures 62P) (see Fig. 7 and Figs. 13A-13B and [0028], [0056]).
Regarding claim 8, LIANG discloses the semiconductor structure of claim 5, further comprising a gate stack (gate layers 90P/90N and gate dielectric layer 88) surrounding the one or more nanosheet channel layers, wherein the dielectric bar is recessed below a top surface of the gate stack (dielectric wall has upper surface lower than upper surface of gate layers 90P/90N).
Furthermore, it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 8 is directed to a device, the method of forming the dielectric bar is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…recessed below” stated in claim 8 has not been given any patentable weight. MPEP 2113 [R-1].
Regarding claim 9, LIANG discloses a semiconductor structure in Figs. 6-7 and 13A-13C, comprising: a substrate (substrate 50) (see Fig. 8A and [0021], [0045]); one or more nanosheet channel layers (nanostructures 56B) disposed over the substrate (see Fig. 8A and [0028]), the one or more nanosheet channel layers providing channels for a complementary metal oxide-semiconductor device (making NFETs and PFETs devices) (see Fig. 6 and [0022], [0024]); and a dielectric bar (dielectric wall 68) attached to the one or more nanosheet channel layers (see Figs. 8A-8B and [0036]); wherein the dielectric bar is not perpendicular to the substrate (dielectric wall 68 has tapered shape with the sidewall is not perpendicular to the surface of substrate 50) (see Fig. 13A-13B).
Regarding claim 10, LIANG discloses the semiconductor structure of claim 9, wherein: the one or more nanosheet channel layers comprise a first set of one or more nanosheet channels (nanostructures 56B in region of one of fin structures 62N) attached to a first side of the dielectric bar (one side of dielectric wall 68) providing channels for a first set of n-type transistors of the complementary metal-oxide semiconductor device (a group of NFETs of one of fin structures 62N) (see Fig. 7 and Figs. 13A-13B and [0024], [0028], [0056]); and a second set of one or more nanosheet channels (nanostructures 56B in region of one of fin structures 62P) attached to a second side of the dielectric bar (another side of dielectric wall 68) providing channels for a first set of p-type transistors of the complementary metal-oxide semiconductor device (a group of PFETs one of fin structures 62P) (see Fig. 7 and Figs. 13A-13B and [0024], [0028], [0056]).
Regarding claim 12, LIANG discloses the semiconductor structure of claim 9, further comprising: one or more additional nanosheet channel layers (another nanostructure 56B) disposed over the substrate providing channels for an additional complementary metal-oxide semiconductor device (see Figs. 7, 13A and [0024], [0028], [0045]); and an additional dielectric bar (another dielectric wall 68) attached to the one or more additional nanosheet channel layers (see Figs. 7, 13A and [0024], [0036], [0038], [0044]), the additional dielectric bar being perpendicular to the substrate (the other dielectric wall 68 has tapered shape with the sidewall is not perpendicular to the surface of substrate 50) (see Fig. 13A-13B).
Regarding claim 13, LIANG discloses the semiconductor structure of claim 12, wherein: the one or more nanosheet channel layers comprise a first set of one or more nanosheet channels (nanostructures 56B in region of one of fin structures 62N) attached to a first side of the dielectric bar (one side of dielectric wall 68) providing channels for an n-type transistors of the complementary metal-oxide semiconductor device (a group of NFETs of one of fin structures 62N) and a second set of one or more nanosheet channels (nanostructures 56B in region of one of fin structures 62P) attached to a second side of the dielectric bar (another side of dielectric wall 68) providing channels for a p-type transistors of the complementary metal-oxide semiconductor device (a group of PFETs one of fin structures 62P) (see Fig. 7 and Figs. 13A-13B and [0024], [0028], [0056]); and the one or more additional nanosheet channel layers comprise a third set of one or more nanosheet channels (nanostructures 56B in region of another one of fin structures 62N) attached to a first side of the additional dielectric bar (one side of another dielectric wall 68) providing channels for an n-type transistors of the additional complementary metal-oxide semiconductor device (a group of NFETs of another one of fin structures 62N) and a fourth set of one or more nanosheet channels (nanostructures 56B in region of another one of fin structures 62P) attached to a second side of the additional dielectric bar (another side of the other dielectric wall 68) providing channels for a p-type transistors of the additional complementary metal-oxide semiconductor device (a group of PFETs another one of fin structures 62P) (see Fig. 7 and Figs. 13A-13B and [0024], [0028], [0056]).
Regarding claim 15, LIANG discloses the semiconductor structure of claim 9, further comprising a gate stack (gate layers 90P/90N and gate dielectric layer 88) surrounding the one or more nanosheet channel layers, wherein the dielectric bar is recessed below a top surface of the gate stack (dielectric wall has upper surface lower than upper surface of gate layers 90P/90N).
Furthermore, it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 15 is directed to a device, the method of forming the dielectric bar is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…recessed below” stated in claim 15 has not been given any patentable weight. MPEP 2113 [R-1].
Regarding claim 16, LIANG discloses the semiconductor structure of claim 9, wherein the complementary metal-oxide-semiconductor device utilizes a forksheet transistor architecture (see [0024]).
Regarding claim 17, LIANG discloses a semiconductor structure in Figs. 6-7 and 13A-13C, comprising: a transistor structure comprising: a substrate (substrate 50) (see Fig. 8A and [0021], [0045]); one or more nanosheet channel layers (nanostructures 56B) disposed over the substrate (see Fig. 8A and [0028]), the one or more nanosheet channel layers providing channels for a complementary metal oxide-semiconductor device (making NFETs and PFETs devices) (see Fig. 6 and [0022], [0024]); and a dielectric bar (dielectric wall 68) attached to the one or more nanosheet channel layers (see Figs. 8A-8B and [0036]); wherein the dielectric bar is not perpendicular to the substrate (dielectric wall 68 has tapered shape with the sidewall is not perpendicular to the surface of substrate 50) (see Fig. 13A-13B).
Regarding claim 18, LIANG discloses the semiconductor structure of claim 17, wherein: the one or more nanosheet channel layers comprise a first set of one or more nanosheet channels (nanostructures 56B in region of one of fin structures 62N) attached to a first side of the dielectric bar (one side of dielectric wall 68) providing channels for a first set of n-type transistors of the complementary metal-oxide semiconductor device (a group of NFETs of one of fin structures 62N) (see Fig. 7 and Figs. 13A-13B and [0024], [0028], [0056]); and a second set of one or more nanosheet channels (nanostructures 56B in region of one of fin structures 62P) attached to a second side of the dielectric bar (another side of dielectric wall 68) providing channels for a first set of p-type transistors of the complementary metal-oxide semiconductor device (a group of PFETs one of fin structures 62P) (see Fig. 7 and Figs. 13A-13B and [0024], [0028], [0056]).
Regarding claim 19, LIANG discloses the semiconductor structure of claim 17, further comprising: one or more additional nanosheet channel layers (another nanostructure 56B) disposed over the substrate providing channels for an additional complementary metal-oxide semiconductor device (see Figs. 7, 13A and [0024], [0028], [0045]); and an additional dielectric bar (another dielectric wall 68) attached to the one or more additional nanosheet channel layers (see Figs. 7, 13A and [0024], [0036], [0038], [0044]), the additional dielectric bar being perpendicular to the substrate (the other dielectric wall 68 has tapered shape with the sidewall is not perpendicular to the surface of substrate 50) (see Fig. 13A-13B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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