Prosecution Insights
Last updated: April 19, 2026
Application No. 18/515,583

DISPLAY DEVICE

Non-Final OA §102§103
Filed
Nov 21, 2023
Examiner
RAABE, CHRISTOPHER M
Art Unit
2875
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
96%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allow Rate
531 granted / 793 resolved
-1.0% vs TC avg
Strong +28% interview lift
Without
With
+28.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
31 currently pending
Career history
824
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
57.1%
+17.1% vs TC avg
§102
35.4%
-4.6% vs TC avg
§112
5.7%
-34.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 793 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1, 2, 4-6, 8-10 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Tak et al (USPN 2023/0041748) . With regard to claim 1 , Tak et al. disclose in at least figures 18, 22 a display device comprising: a first base substrate (SUB) ; a display structure (PXA) on the first base substrate; a bank portion (BNK) on the display structure and defining a pixel opening (in PXA) and a dummy opening (in DPXA) adjacent to the pixel opening; a color conversion layer (CCL) in the pixel opening of the bank portion; and a capping layer (CPL1, CPL2 , INS4 ) covering the bank portion and the color conversion layer and including: a first layer (CPL1) on the bank portion and including silicon oxide (See paragraph 240) ; and a second layer (CPL2) on the first layer and including silicon oxynitride in the dummy opening (See paragraph 245) . With regard to claim 2 , Tak et al. disclose t he display device of claim 1, wherein the first layer (CPL1) directly contacts a side surface of the bank portion in the dummy opening ( see figs 22, without INS4 , paragraph 235 ) . With regard to claim 4 , Tak et al. disclose t he display device of claim 1, wherein the dummy opening includes seven or less sub-dummy openings (DPXL, see figs. 4) . With regard to claim 5 , Tak et al. disclose t he display device of claim 4, wherein a shape of each of the sub-dummy openings (DPXL) is a circle or a polygon with eight sides or less in a plan view (see figs. 4) . With regard to claim 6 , Tak et al. disclose t he display device of claim 4, wherein a shape of each of the sub-dummy openings (DPXL) is a polygon and corners of the polygon are rounded in a plan view (see figs. 4) . With regard to claim 8 , Tak et al. disclose t he display device of claim 1, wherein the capping layer includes: a third layer (CPL2, taking INS4 as first layer and CPL1 as second) on the second layer and including silicon oxide (See paragraphs 240,245222,235) . With regard to claim 9 , Tak et al. disclose t he display device of claim 1, further comprising: a second base substrate (BSL) facing the first base substrate; a color filter layer (CF) under the second base substrate; and a filling layer (SL) between the color filter layer and the capping layer. With regard to claim 10 , Tak et al. disclose t he display device of claim 1, wherein the display structure includes: a driving element (T) on the first base substrate; a light emitting diode (LD) on the driving element and connected to the driving element; and an encapsulation layer (INS3) on the light emitting diode. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim s 3, 11-17, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tak et al. (as above) . With regard to claim 3 , Tak et al. disclose t he display device of claim 2 . While Tak et al. is silent as to the thickness of the capping layers, a thickness range in a range of 1500 Å and 10000 Å is commensurate with devices as disclosed by Tak et al. and would have been obvious to one of ordinary skill in the art at the time of the invention to try in order to optimize, balancing protective function while maintaining a thin device. With regard to claim 11 , Tak et al. disclose a display device comprising: a first base substrate (SUB) ; a display structure (PXA) on the first base substrate; a bank portion (BNK) on the display structure and defining a pixel opening (in PXA) and a dummy (in DPXA) opening adjacent to the pixel opening; a color conversion layer (CCL) in the pixel opening of the bank portion; and a capping layer (CPL1, CPL2) covering the bank portion and the color conversion layer and including a first layer (CPL1) on the bank portion, including silicon oxide (see paragraph 240) in the dummy opening . While Tak et al. is silent as to the thickness of the capping layers, a thickness range in a range of 1500 Å and 10000 Å is commensurate with devices as disclosed by Tak et al. and would have been obvious to one of ordinary skill in the art at the time of the invention to try in order to optimize, balancing protective function while maintaining a thin device. With regard to claim 12 , Tak et al. disclose t he display device of claim 11, wherein the first layer (CPL1) directly contacts a side surface of the bank portion (without INS4 paragraph 235) in the dummy opening (See figs 22) . With regard to claim 13 , Tak et al. disclose t he display device of claim 12, wherein the thickness range of the first layer is a thickness range of a part overlapping a side surface of the bank portion (see figs. 22) . With regard to claim 14 , Tak et al. disclose t he display device of claim 12, wherein the capping layer further includes: a second layer (CPL2) on the first layer and including silicon oxide (see paragraph 245) . With regard to claim 15 , Tak et al. disclose t he display device of claim 11, wherein the dummy opening includes seven or less sub-dummy openings (DPXL see figs 4) . With regard to claim 16 , Tak et al. disclose t he display device of claim 15, wherein a shape of each of the sub-dummy openings is a circle or a polygon with eight sides or less in a plan view (see figs 4) . With regard to claim 17 , Tak et al. disclose t he display device of claim 16, wherein when a shape of each of the sub-dummy openings a polygon, a corner of the polygon is rounded (See figs. 4) . With regard to claim 19 , Tak et al. disclose t he display device of claim 11, further comprising: a second base substrate (BSL) facing the first base substrate; a color filter layer (CF) under the second base substrate; and a filling layer (SL) between the color filter layer and the capping layer. With regard to claim 20 , Tak et al. disclose t he display device of claim 11, wherein the display structure includes: a driving element (T) on the first base substrate; a light emitting diode (LD) on the driving element and connected to the driving element; and an encapsulation layer (INS3) on the light emitting diode. Claim s 7,18 are rejected under 35 U.S.C. 103 as being unpatentable over Tak et al. (as above), in view of Lee et al. (USPN 2021/0202852) . With regard to claim 7 , 18, Tak et al. disclose t he display device of claim 1, 11, further comprising: a sub-capping layer (INS4) between the bank portion and the capping layer (See figs22) , including silicon oxynitride (See paragraphs 222,235) . While Tak et al. is silent as to the nitrogen content of the silicon oxynitride, Lee et al. does disclose a protective layer of silicon oxynitride having a nitrogen content in a range of 10 at % to 40 at % in the silicon oxynitride (see paragraph 106). It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate this concept of Lee et al. into the device of Tak et al. in order to provide the silicon oxynitride of Tak et al . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. USPN 2022/0328581, 2022/0157893, 2023/0030101, 2023/0282682, 2023/0148430, KR20190081909. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Christopher Raabe whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-8434 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 0530-1430 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT James R Greece can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)272-3711 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER M RAABE/ Primary Examiner, Art Unit 2875
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Prosecution Timeline

Nov 21, 2023
Application Filed
Mar 15, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
96%
With Interview (+28.5%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 793 resolved cases by this examiner. Grant probability derived from career allow rate.

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