DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang et al. (U.S. Pub. 2020/0273806) [Hereafter “Chiang”].
Regarding claim 1, Chiang [Figs.1-11] discloses a semiconductor package, comprising:
a lower redistribution wiring layer [150] having a first region [central region] and a second region [peripheral region] adjacent the first region, the lower redistribution wiring layer including first redistribution wirings [Fig.7];
a semiconductor chip [130] on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings [Fig.11];
a sealing member [140] on a side surface of the semiconductor chip [130] on the lower redistribution wiring layer [150] [Fig.11];
a plurality of vertical conductive structures [120] penetrating the sealing member [140] on the second region of the lower redistribution wiring layer [150] and electrically connected to the first redistribution wirings [Fig.11];
a marking pattern [1141] on the semiconductor chip [130];
seed layer pads [1142] [Fig.4; Paras.16-18] on respective end portions of the vertical conductive structures [120] that are exposed by the sealing member at an upper surface thereof; and
an upper redistribution wiring layer [110/112’] on the sealing member and the marking pattern, the upper redistribution wiring layer including second redistribution wirings [1142/170] electrically connected to the plurality of vertical conductive structures [120].
Regarding claim 9, Chiang [Figs.1-11] discloses a semiconductor package
wherein the marking pattern [1141] is attached on a backside of the semiconductor chip [130] by an adhesive film [136], wherein the backside of the semiconductor chip is opposite the lower redistribution wiring layer [150].
Claim(s) 1 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pei et al. (U.S. Pub. 2019/0148262) [Hereafter “Pei”].
Regarding claims 1 and 10, Pei [Figs.1-8] discloses a semiconductor package, comprising:
a lower redistribution wiring layer [140] having a first region [central region] and a second region [peripheral region] adjacent the first region, the lower redistribution wiring layer including first redistribution wirings [143,145,147] [Fig.4];
a semiconductor chip [120] on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings [Fig.4];
a sealing member [130] on a side surface of the semiconductor chip [120] on the lower redistribution wiring layer [140] [Fig.8];
a plurality of vertical conductive structures [119] penetrating the sealing member [130] on the second region of the lower redistribution wiring layer [140] and electrically connected to the first redistribution wirings [Fig.8];
a marking pattern [112] [Figs.1-3] on the semiconductor chip [120];
seed layer pads [115] [Fig.1; Paras.16,19] on respective end portions of the vertical conductive structures [119] that are exposed by the sealing member at an upper surface thereof; and
an upper redistribution wiring layer [110/168] on the sealing member and the marking pattern, the upper redistribution wiring layer including second redistribution wirings [114/168] electrically connected to the plurality of vertical conductive structures [119];
wherein the semiconductor chip [120] is a first semiconductor chip of a first package, and further comprising:
a second package [160] on the upper redistribution wiring layer [110/168],
wherein the second package includes a package substrate [161] and at least one second semiconductor chip [162] stacked on the package substrate [Fig.8].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 and 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pei et al. (U.S. Pub. 2019/0148262) in view of Chen et al. (U.S. Pub. 2015/0270247) [Hereafter “Chen”].
Regarding claims 2-3 and 5-7, Pei fails to explicitly disclose the limitations of the claims. However, Chen [Figs.1A-D] discloses a semiconductor package
wherein an upper surface of the marking pattern [106] is coplanar with the upper surface of the sealing member [114];
wherein an upper surface of the seed layer pad [Pad region of vertical conductive structure 108] is coplanar with or lower than the upper surface of the sealing member [114];
wherein the marking pattern [106] includes a first seed layer and a second seed layer stacked on the first seed layer [Para.17];
wherein the first seed layer includes copper, and the second seed layer includes titanium [Para.17];
wherein the seed layer pads respectively comprise the first seed layer and the second seed layer stacked on the first seed layer, or wherein the seed layer pads respectively comprise the first seed layer [Paras.17,20].
It would have been obvious to provide the mark pattern as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (U.S. Pub. 2020/0273806).
Regarding claim 8, Chiang fails to explicitly disclose the thickness of the marking pattern. However, the marking pattern 1121 formed in the dummy pattern 1141 of Chiang serves a same purpose (represent information on a manufacturer, date of manufacture, serial number, and the like) as the marking pattern 420 of the claimed invention, it would be obvious to provide wherein the marking pattern has a thickness of about 0.1 micrometers (µm) to about 0.5 µm. It would have been obvious since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 11 and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pei et al. (U.S. Pub. 2019/0148262) in view of Chen et al. (U.S. Pub. 2015/0270247).
Regarding claim 11, Pei [Figs.1-8] discloses a semiconductor package, comprising:
a lower redistribution wiring layer [140] including first redistribution wirings;
a semiconductor chip [120] on the lower redistribution wiring layer, wherein a first surface of the semiconductor chip comprising chip pads [128] [Fig.3] faces the lower redistribution wiring layer [Fig.4];
a sealing member [130] on the semiconductor chip [120] and on the lower redistribution wiring layer [140], wherein the sealing member exposes a second surface of the semiconductor chip opposite to the first surface [Fig.4];
a plurality of vertical conductive structures [119] penetrating the sealing member and electrically connected to the first redistribution wirings;
a marking pattern [112] on the second surface of the semiconductor chip; and
an upper redistribution wiring layer [110,168] on the sealing member and the marking pattern, the upper redistribution wiring layer including second redistribution wirings [114,168] electrically connected to the plurality of vertical conductive structures [Fig.8].
Pei fails to explicitly disclose wherein an upper surface of the marking pattern is coplanar with an upper surface of the sealing member. However, Chen [Figs.1A-D] discloses a semiconductor package wherein an upper surface of the marking pattern [106] is coplanar with an upper surface of the sealing member [114]. It would have been obvious to provide wherein an upper surface of the marking pattern is coplanar with an upper surface of the sealing member, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 16-19, Pei fails to explicitly disclose the limitations of the claims. However, Chen [Figs.1A-D] discloses a semiconductor package
further comprising:
seed layer pads [Pad region of vertical conductive structure 108] [Paras.17,20] on respective end portions of the vertical conductive structures that are exposed by the sealing member [114] at the upper surface thereof;
wherein upper surfaces of the seed layer pads [Pad region of vertical conductive structure 108] [Paras.17,20] are coplanar with or lower than the upper surface of the sealing member [114];
wherein the sealing member [114] is on side surfaces of the seed layer pads [Pad region of vertical conductive structure 108] [Paras.17,20] [Fig.1D];
wherein: the seed layer pads respectively comprise a first seed layer and a second seed layer stacked on the first seed layer, or the seed layer pads respectively comprise the first seed layer [Pad region of vertical conductive structure 108] [Paras.17,20]; and
wherein the marking pattern [106] comprises the first seed layer and the second seed layer [Para.17].
It would have been obvious to provide the seed layer pads and the marking pattern as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claims 21, 24, and 28-30 are allowed.
The following is an examiner’s statement of reasons for allowance: Prior art does not fairly disclose or make obvious the claimed device/method taken as a whole, and specifically, the limitations of
a lower redistribution wiring layer having a first region and a second region adjacent the first region, the lower redistribution wiring layer including first redistribution wirings;
a semiconductor chip on the first region of the lower redistribution wiring layer, wherein a first surface of the semiconductor chip comprising chip pads faces the lower redistribution wiring layer;
a sealing member on the semiconductor chip and on the lower redistribution wiring layer, wherein the sealing member exposes a second surface of the semiconductor chip opposite to the first surface;
a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings;
a marking pattern on the second surface of the semiconductor chip;
seed layer pads on respective end portions of the vertical conductive structures that are exposed by the sealing member at an upper surface thereof; and
an upper redistribution wiring layer on the sealing member and the marking pattern, the upper redistribution wiring layer including second redistribution wirings on the seed layer pads,
wherein the sealing member is on a side surface of the marking pattern and is on side surfaces of the seed layer pads.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not fairly disclose or make obvious the claimed device/method taken as a whole, and specifically, the limitations of
wherein the sealing member is on a side surface of the marking pattern.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BAC H AU/Primary Examiner, Art Unit 2898