DETAILED ACTION
This action is responsive to the amendment filed December 3, 2025. Claims 1-20 are pending. Claims 1, 3-10, and 12-20 have been amended. Claims 1, 10, and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation - general
Regarding the term "word line setup period" recited in claims 1, 3, and 5-10, it is noted that the term is instantiated a total of 16 times in the Specification but is not explicitly defined in the instant application. A word line setup period is well understood in the art as "the time period prior to a program, erase or read operation during which the voltages of the transistors of the 3D memory stack are prepared to overcome the large RC delays prior to executing the memory operation.” Since memory operations may logically occur in any order or sequence, the word line setup period will be understood using the broadest reasonable interpretation to mean any time prior to, and other than, during a program, erase, or read operation.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-7, and 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Joe et al. (US 20200381065; "Joe" – of Record) in view of Kim et al. (US 20140347927; "Kim") and further in view of Kwon (US 20100246259 – of Record) and further in view of Seo et al. (US 20220020438; "Seo" – of Record) and further in view of Joo et al. (US 20200395075; "Joo").
Regarding independent claim 1, Joe discloses a method of operating a memory device comprising
a plurality of word lines (Fig. 6 WL1-WL8),
a plurality of string select lines (Fig. 6 SSL1-SSL3),
a plurality of ground select lines (Fig. 6 GSL1-GSL3),
a plurality of strings selectively connected to a common source line and are operatively connected with the plurality of word lines (Fig. 6. where it illustrates string NS11 and NS12 connected to CSL and WL1-WL8),
and a plurality of string select lines to selectively connect at least one bit line to the plurality of strings (Fig. 6. where it illustrates string select lines SSL1 and SSL2 and SSL1 connects bit line BL1 to string NS11),
wherein the plurality of strings includes a selected string, and a first unselected string, and at least one second unselected string (Fig. 10A where it illustrates VSSL_SEL and VSSL_Unsel indicating both selected and unselected strings. See also para. 91; " partial cell strings on which the precharge operation is performed may be the non-selection cell strings." indicating that there are more than one unselected strings),
the method comprising:
applying an on-voltage to the second ground select line at a first time point during the word line setup period to connect the common source line to the at least one second unselected string (Fig. 12B where it illustrates the turn on voltage VGSL applied to the ground select line during the first time (precharge). See also para. 37; "As another example, the precharge voltage may be applied to the non-selection cell string through a common source line". It is noted that an "unselected ground select line" is taken to mean it is part of the non-selection cell string, and the ground selection transistor must necessarily be on for the string to precharge through the common source line);
applying an on-voltage to string select lines connected to the selected string and the first unselected string during the word line setup period (Fig. 13B where it depicts VSSL for the selected and unselected string select lines ramping to ON during the word line setup period);
and applying a ground voltage to the common source line at a fourth time point during the word line setup period (Fig. 12B where it illustrates VCSL going to ground at a fourth time (T4)),
wherein the first time point, second time point, third time point and fourth time point occur sequentially in that order (Fig. 12B where it illustrates time periods t1 through t4 for example. As noted in the claim interpretation section above, the word line setup period will be understood using the broadest reasonable interpretation to mean any time other than during a program, erase, or read operation and since memory operations may logically occur in any order or sequence, will necessarily occur in that order).
While the structure of Joe includes ground select lines, it is silent about split ground lines shared by a plurality of strings.
However, Kim teaches a memory device comprising
and the plurality of ground select lines includes a first ground select line to selectively connect the selected string and the first unselected string to the common source line (Fig. 6 where it illustrates a first ground select line (GSL 0) connected to the selected string (240) and first unselected string (230), which are connected to the common source line (CSL))
and a second ground select line to selectively connect the at least one second unselected string to the common source line (Fig. 6 where it illustrates the second ground select line (GSL1) connected to the second unselected string (250), which is connected to the common source line (CSL)),
While the structure of Joe and Kim disclose selected and unselected word lines, they are silent about explicitly applying voltages to both during a word line setup period.
However, Kwon teaches the method comprising
applying voltages to a plurality of unselected word lines and a selected word line included in the plurality of word lines during a word line setup period;(Fig. 5: S110. See also para. 83; "the program controller 251 initially controls the application of the first pass voltage Vpass1 to the selected word line (i.e., the "selection word line", or WL6 in the illustrated example) as well as to the non-selected word line (i.e., the "non-selection word line", or WL3 in the illustrated example) (S110)))
While the structure of Joe, Kim, and Kwon also disclose a common source line, they are silent with regard to specific sequencing of the split ground select lines.
However, Seo teaches applying an off-voltage to the first ground select line at the first time point to disconnect the common source line to the selected string and the first unselected string (Fig. 8 where it illustrates the voltage for the select string GSL dropping to GND (OFF) at t5);
While the structures of Joe, Kim, Kwon, and Seo also disclose ground select lines and common source lines, they are silent with incorporating the sequencing of the common source line with the sequencing of the ground select lines.
However, Joo teaches applying a first voltage to the common source line at a second time point during the word line setup period to charge the unselected string that is connected to the common source line (Fig. 7C where it illustrates having voltage Vpre applied to CSL during the word line setup period (P1) along with the unselected strings (unsel_SSL). As the string select lines (unsel_DSL) are off, it would necessarily charge the unselected string);
applying an off-voltage to the second ground select line at a third time point during the word line setup period (Fig. 7C where it illustrates ground select line unsel_SSL going to ground (off) at T3 during the word line setup period (P1));
Joe, Kim, Kwon, and Seo along with Joo are from the same field of endeavor as applicant’s invention directed to operating NAND memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Joe's basic vertical NAND string structure with the teachings of Kim's use of split ground select lines with the teachings of Kwon's applying voltages to both the selected and unselected word lines with the teachings of Seo's sequencing of the split ground select lines with the teachings of Joo's integration of sequencing the common source line. Doing so would speed up memory operations, provide greater addressing granularity and reduce operational disturbance.
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Regarding claim 2, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 1.
As applied, Kwon further discloses wherein a voltage rising slope of the plurality of word lines is greater in a time period after the second time point than in a time period before the second time point (Fig. 11. See also Examiner's Markup above).
Regarding claim 3, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 1.
As applied, Seo further discloses further comprising:
applying the on-voltage to the first ground select line at the fourth time point where the fourth time point corresponds to the beginning of a sensing period and an end to the word line setup period (Fig. 18 where it illustrates the selected ground select line at the start of the 1st sense/read period);
applying a first read voltage to the selected word line during a first time period of the sensing period (Fig. 18 where it illustrates the voltage Vr1 applied on the selected word line at a start of a 1st sense/read period (t1));
applying a second read voltage to the selected word line during a second time period of the sensing period (Fig. 18 where it illustrates the voltage Vr2 applied to the selected word line during the second time period (t3));
and selectively applying the on-voltage to the second ground select line based on characteristics of the selected word line during the second time period (Fig. 18 where it illustrates the pulse on the unselected ground select line at the start of the 2nd sense/read period. It is noted that this limitation appears directed toward Fig. 15 and para. 129-132 of the instant application and specifically, where it states: " FIG. 15, after the first sensing period ends, a pre-pulse may be applied to the ground select line GSL2 at a sixth time point t16." The time point t16 is the start of the 2nd sensing period and the pulse at that time are both analogous to Seo. Regarding the basis characteristic of the selected word line, it is observed that there is no structure claimed nor means disclosed in the instant application which indicates or determines that characteristic or if it may even be predetermined during manufacturing or test of the device and thus a static condition. Further, while the specification conveys various examples of what the characteristic may be, there are no specific metes and bounds to define the full scope of this feature. Therefore, the limitation for this claim will be understood using the broadest reasonable interpretation to mean that the selected word line exists and exhibits some static material property).
Regarding claim 4, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 3.
As applied, Seo further discloses wherein
the characteristics of the selected word line include at least one of (As noted above, the claimed characteristic is taken to mean exhibiting some static material property)
a stacking position of the selected word line among the plurality of word lines (para. 6; "a non-volatile memory device including: a memory cell array which includes", "a first memory cell and a first ground select transistor stacked sequentially in a first direction", "wherein a first word line is connected to the first memory cell". It is noted that whatever memory cell is selected, it would exist, and it's word line would necessarily exhibit the static material property of a position within the stack).
a width of a channel hole for a channel of the selected word line,
a distance between the channel and an end of the selected word line,
a thickness of an insulating layer between the selected word line and the channel,
or a voltage level applied to the selected word line during the sensing period.
Regarding claim 5, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 1.
As applied, Seo further discloses further comprising:
applying the on-voltage to an unselected string select line connected to the at least one second unselected string during the word line setup period (Fig. 8 where it illustrates the voltage for the unselect string GSL ramping to Vgsl3 (ON) at t5 and thus discharging).
Regarding claim 6, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 1.
As applied, Seo further discloses further comprising:
maintaining the voltage of a string select line connected to the at least one second unselected string at the off-voltage during the word line setup period (Fig. 8 where it illustrates the unselected string select line SSL UnSel at the off voltage (GND) between at least t5 through t7).
Regarding claim 7, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 1.
As applied, Joe further discloses further comprising:
recovering the selected word line after applying a program voltage to the selected word line during a program period before the word line setup period (Fig. 12B where it illustrates the selected word line going from the program voltage (T1-T2) to ground during the recovery period (T2-T3));
recovering the selected word line after applying the on-voltage to the first ground select line and the second ground select line during the program period (Fig. 12B where it illustrates the ground select lines have the on- voltage applied during the program period (T1-T2));
and after applying the first voltage to the common source line during the program period, maintaining the applied first voltage until the fourth time point (Fig. 12B where it shows the common source line being precharged to VCSL1 during the program period and maintaining that voltage until the fourth time period (T4)).
Regarding independent claim 10, Joe discloses a memory device comprising:
a memory cell array comprising a plurality of strings selectively connected to a common source line (Fig. 6 NS11-NS33 which connect to CSL);
a plurality of word lines operatively connected to the plurality of strings (Fig. 6 WL1-WL8);
a plurality of string select lines connected to the plurality of strings, wherein the plurality of strings includes a selected string, a first unselected string, and at least one second unselected string (Fig. 10A where it illustrates VSSL_SEL and VSSL_Unsel indicating both selected and unselected strings. See also para. 91; " partial cell strings on which the precharge operation is performed may be the non-selection cell strings." indicating that there are more than one unselected strings);
and control circuitry (Fig. 4:130 control logic. It is noted that the control logic would apply voltages to all the word lines for all phases of all operations) configured to control to:
apply an on-voltage to the second ground select line at a first time point to connect the common source line to the at least one second string (Fig. 12B where it illustrates the turn on voltage VGSL applied to the ground select line during the first time (precharge). See also para. 37; "As another example, the precharge voltage may be applied to the non-selection cell string through a common source line". It is noted that an "unselected ground select line" is taken to mean it is part of the non-selection cell string, and the ground selection transistor must necessarily be on for the string to precharge through the common source line.),
apply an on-voltage to string select lines connected to the selected string and the first unselected string during the word line setup period (Fig. 13B where it depicts VSSL for the selected and unselected string select lines ramping to ON during the word line setup period),
and apply a ground voltage to the common source line at a fourth time point (Fig. 12B where it illustrates VCSL going to ground at a fourth time (T4)).
wherein the first time point, second time pint, third time point, and fourth time point occur sequentially in that order (Fig. 12B where it illustrates time periods t1 through t4 for example. As noted in the claim interpretation section above, the word line setup period will be understood using the broadest reasonable interpretation to mean any time other than during a program, erase, or read operation and since memory operations may logically occur in any order or sequence, will necessarily occur in that order).
While the structure of Joe includes ground select lines, it is silent about split ground lines shared by a plurality of strings.
However, Kim teaches a plurality of ground select lines connected to the plurality of strings, wherein the plurality of ground select lines includes a first ground select line to selectively connect the selected string and first unselected string to the common source line (Fig. 6 where it illustrates a first ground select line (GSL 0) connected to the selected string (240) and first unselected string (230), which are connected to the common source line (CSL))
and a second ground select line to selectively connect the at least one second unselected string to the common source line (Fig. 6 where it illustrates the second ground select line (GSL1) connected to the second unselected string (250), which is connected to the common source line (CSL));
While the structure of Joe and Kim disclose selected and unselected word lines, they are silent about explicitly applying voltages to both during a word line setup period.
However, Kwon teaches apply voltages to a plurality of unselected word lines and a selected word line of the plurality of word lines of a selected string of the plurality of strings during a word line setup period (Fig. 5: S110. See also para. 83; "the program controller 251 initially controls the application of the first pass voltage Vpass1 to the selected word line (i.e., the "selection word line", or WL6 in the illustrated example) as well as to the non-selected word line (i.e., the "non-selection word line", or WL3 in the illustrated example) (S110))),
While the structure of Joe, Kim, and Kwon also disclose a common source line, they are silent with regard to specific sequencing of the split ground select lines.
However, Seo teaches apply an off-voltage to the first ground select line at the first time point to disconnect the common source line to the selected string and the first unselected string (Fig. 8 where it illustrates the voltage for the select string GSL dropping to GND (OFF) at t5);
While the structures of Joe, Kim, Kwon, and Seo also disclose ground select lines and common source lines, they are silent with incorporating the sequencing of the common source line with the sequencing of the ground select lines.
However, Joo teaches apply a first voltage to the common source line at a second time point during the word line setup period to charge the unselected string that is connected to the common source line (Fig. 7C where it illustrates having voltage Vpre applied during the word line setup period (P1) along with the unselected strings (unsel_SSL). As the string select lines (unsel_DSL) are off, it would necessarily charge the unselected string),
apply an off-voltage to the second ground select line at a third time point (Fig. 7C where it illustrates ground select line unsel_SSL going to ground (off) at T3 during the word line setup period (P1)),
Joe, Kim, Kwon, and Seo along with Joo are from the same field of endeavor as applicant’s invention directed to operating NAND memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Joe's basic NAND string structure with the teachings of Kim's split ground select lines with the teachings of Kwon's applying voltages to both the selected and unselected word lines with the teachings of Seo's sequencing of the split ground select lines with the teachings of Joo's integration of sequencing the common source line. Doing so would speed up memory operations, provide greater addressing granularity and reduce operational disturbance.
Regarding claim 11, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 10.
As applied, Kwon further discloses wherein the voltage of the plurality of word lines is increased to a first voltage at the second time point, and the voltage of the plurality of word lines is increased to a second voltage higher than the first voltage at a fifth time point between the second time point and the third time point (Fig. 11. Selected WL6 where the "fifth time point is" between T2 and T3).
Regarding claim 12, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 10.
As applied, Seo further discloses wherein a first read voltage is applied to a selected word line during a first time period after the fourth time point (Fig. 18 where it illustrates the voltage Vr1 applied on the selected word line at a start of a 1st sense/read period (t1).),
a second read voltage is applied to the selected word line during a second time period after the first time period (Fig. 18 where it illustrates the voltage Vr2 applied to the selected word line during the second time period (t3)),
and wherein the on-voltage is applied to the second ground select line during the second time period based on characteristics of the selected word line (Fig. 18 where it illustrates the pulse on the unselected ground select line at the start of the 2nd sense/read period. It is noted that this limitation appears directed toward Fig. 15 and para. 129-132 of the instant application and specifically, where it states: " FIG. 15, after the first sensing period ends, a pre-pulse may be applied to the ground select line GSL2 at a sixth time point t16." The time point t16 is the start of the 2nd sensing period and the pulse at that time are both analogous to Seo. Regarding the basis characteristic of the selected word line, it is observed that there is no structure claimed nor means disclosed in the instant application which indicates or determines that characteristic or if it may even be predetermined during manufacturing or test of the device and thus a static condition. Further, while the specification conveys various examples of what the characteristic may be, there are no specific metes and bounds to define the full scope of this feature. Therefore, the limitation for this claim will be understood using the broadest reasonable interpretation to mean that the selected word line exists and exhibits some static material property.).
Regarding claim 13, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 12.
As applied, Seo further discloses wherein the characteristics of the selected word line include: at least one of (As noted above, the claimed characteristic is taken to mean exhibiting some static material property)
at least one of a stacking position of the selected word line (para. 6; "a non-volatile memory device including: a memory cell array which includes", "a first memory cell and a first ground select transistor stacked sequentially in a first direction", "wherein a first word line is connected to the first memory cell". It is noted that whatever memory cell is selected, it would exist, and it's word line would necessarily exhibit the static material property of a position within the stack),
a width of a channel hole for a channel of the selected word line,
a distance between the channel and an end of the selected word line,
a thickness of an insulating layer between the selected word line and the channel,
or a voltage level applied to the selected word line during the second time period.
Regarding claim 14, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 10.
As applied, Seo further discloses wherein at the first time point, the off-voltage is applied to a string select line connected to the at least one second string (Fig. 8 where it illustrates the unselected string select line SSL UnSel at the off voltage (GND) between at least t5 through t7).
Regarding claim 15, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 10.
As applied, Joe further discloses wherein, at the first time point, the on-voltage is applied to a string select line connected to the at least one second string (Fig. 13B where it depicts VSSL for the selected and unselected string select lines ramping to ON during the word line setup period).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Joe et al. (US 20200381065; "Joe" – of Record) in view of Kim et al. (US 20140347927; "Kim") and further in view of Kwon (US 20100246259 – of Record) and further in view of Seo et al. (US 20220020438; "Seo" – of Record) and further in view of Joo et al. (US 20200395075; "Joo") as supported by Oh et al. (US 20090287879; "Oh" – of Record).
Regarding claim 8, Joe, Kim, Kwon, Seo and Joo disclose the limitations of claim 1.
As applied, Joe further discloses wherein the at least one second unselected string comprises:
a first transistor connected to the first ground select line and having a first threshold voltage (Fig. 6 where it illustrates the floating gate transistor GST in string NS11 connected to the first ground select line GSL1),
and a second transistor connected to the second ground select line and having a second threshold voltage higher than the first threshold voltage (Fig. 6 where it illustrates the bottom floating gate transistor in string NS 21 connected to the second ground select line GSL2. It is noted that since both the first and second GSTs are of the floating gate type, they are by definition, programmable and could therefore have a first and second threshold voltage. Programming the ground selection transistors is well understood in the art as supported by Oh (Absr. "The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable"). It is further noted that the first transistor could even be programmed to have a negative threshold voltage. It is also observed that there is no structure claimed nor means disclosed in the instant application which indicates or demonstrates how or when the ground select transistors would be programmed, just that they may be programmed (Spec. para. 151). However, since the structure of the memory device as illustrated in Figure 4 of the instant application is substantially identical to the structure of the memory device in Joe's Figure 10, it would be understood by one of ordinary skill in the art that they would be analogous in the ability to program the respective ground select transistors and therefore have similar function.),
wherein the applying of the on-voltage to the unselected ground select line at the first time point during the word line setup period comprises:
applying a voltage having a level between the first threshold voltage and the second threshold voltage to the first ground select line (Fig. 10A where it illustrates the ground selection line at a ground voltage. It is noted that this limitation appears to be directed to Fig. 20 of the instant application which indicates that the voltage applied between the first and second threshold voltage is Voff which is defined in the specification as an "off-voltage". As noted above, the first ground selection transistor of Joe may be programmed with a negative threshold voltage and the second ground selection transistor of Joe may be programmed with a positive threshold voltage just as in the instant application. Thus, Joe's ground voltage on the first ground selection line would be between the two threshold voltages and also be an "off-voltage" for the second ground select line),
and applying a voltage having a level equal to or higher than the second threshold voltage to the second ground select line (Fig. 12B where it illustrates the turn on voltage VGSL applied to the ground select line during the first time (precharge). See also para. 37; "As another example, the precharge voltage may be applied to the non-selection cell string through a common source line". It is noted that an "unselected ground select line" is taken to mean it is part of the non-selection cell string, and the ground selection transistor must necessarily be on for the string to precharge through the common source line.).
Regarding claim 9, Joe, Kim, Kwon, Seo and Joo as supported by Oh disclose the limitations of claim 8.
As applied, Seo further discloses wherein the applying of the off-voltage to the second ground select line at the third time point during the word line setup period comprises:
applying a voltage having a level higher than the second threshold voltage to the first ground select line, and applying a voltage having a level between the first threshold voltage and the second threshold voltage to the second ground select line (Fig. 15 where it shows the unselected ground select line off prior to the sensing period (t2). It is noted that this combination of GSL voltages in the instant application effectively disconnects the GST from the common source line CSL just prior to the 1st sensing period as disclosed in para. 159 of the specification.).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Joe et al. (US 20200381065; "Joe" – of Record) in view of Kim et al. (US 20140347927; "Kim") and further in view of Seo et al. (US 20220020438; "Seo" – of Record) and further in view of Joo et al. (US 20200395075; "Joo").
Regarding independent claim 16, Joe discloses a method of operating a memory device comprising:
a plurality of word lines (Fig. 6 WL1-WL8),
a plurality of string select lines (Fig. 6 SSL1-SSL3),
a plurality of ground select lines (Fig. 6 GSL1-GSL3),
a plurality of strings selectively connected to a common source line (Fig. 6. where it illustrates string NS11 and NS12 connected to common source line CSL),
and a plurality of string select lines (Fig. 6 SSL1-SSL3),
wherein the plurality of strings includes a selected string, a first unselected string, and at least one second unselected string (Fig. 10A where it illustrates VSSL_SEL and VSSL_Unsel indicating both selected and unselected strings. See also para. 91; " partial cell strings on which the precharge operation is performed may be the non-selection cell strings." indicating that there are more than one unselected strings),
the method comprising:
applying voltages to a plurality of word lines (Fig. 6 WL(SEL) and WL(UnSEL));
applying an on-voltage to string select lines connected to the selected string and the first unselected string (Fig. 13B where it depicts VSSL for the selected and unselected string select lines ramping to ON during the word line setup period);
While the structure of Joe includes ground select lines, it is silent about split ground lines shared by a plurality of strings and sensing read data.
However, Kim teaches a memory device comprising
and the plurality of ground select lines includes a first ground select line to selectively connect the selected string and first unselected string to the common source line (Fig. 6 where it illustrates a first ground select line (GSL 0) connected to the selected string (240) and first unselected string (230), which are connected to the common source line (CSL))
and a second ground select line to selectively connect the at least one second unselected string to the common source line (Fig. 6 where it illustrates the second ground select line (GSL1) connected to the second unselected string (250), which is connected to the common source line (CSL)),
and sensing data by applying a read voltage to a selected word line among the plurality of word lines (Fig. 1. See also para. 36; "In a read operation, page buffer 130 senses data stored in the selected memory cell through bit lines". And see para. 34; "In a read operation, row decoder 120 transfers a selection read voltage Vrd to the selected word line")
While the structure of Joe and Kim also discloses ground select lines, they are silent with regard to specific sequencing of ground select lines.
However, Seo teaches applying an on-voltage to the second ground select line while maintaining an off-voltage to the first ground select line (Fig. 8 where it illustrates the voltage for the ground select line GSL (UnSEL) at Gsl3 while dropping and maintaining GSL (SEL) to GND (OFF));
While the structures of Joe, Kim, and Seo also disclose ground select lines and common source lines, they are silent with incorporating the sequencing of the common source line with the sequencing of the ground select lines.
However, Joo teaches applying a voltage to the common source line while maintaining the second ground select line at an on-voltage and the first ground select line at an off-voltage (Fig. 7C where it illustrates voltage Vpre on CSL at t3 while sel_SSL is at Von and unsel_SSL is at Voff);
applying an off-voltage to the second ground select line (Fig. 7C where it illustrates sel_SSL going to Voff after T5);
applying a ground voltage to the common source line (Fig. 7C where it illustrates CSL going to a ground voltage at T4);
applying an on-voltage to the first ground select line while applying the ground voltage to the common source line (Fig. 7B where it illustrates sel_SSL going to Vssl while CSL is at a ground voltage);
Joe, Kim, and Seo along with Joo are from the same field of endeavor as applicant’s invention directed to operating NAND memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Joe's basic NAND string structure with the teachings of Kim's split ground select with the teachings of Seo's sequencing of the split ground select lines with the teachings of Joo's integration of sequencing the common source line. Doing so would speed up memory operations by reducing loading of the word lines in a vertical NAND flash memory device (Kim, para. 6).
Regarding claim 17, Joe, Kim, Seo and Joo disclose the limitations of claim 16.
As applied, Seo further discloses wherein the sensing of the data comprises:
applying a first read voltage to the selected word line during a first time period (Fig. 18 where it illustrates the voltage Vr1 applied on the selected word line at a start of a 1st sense/read period (t1).
applying a second read voltage to the selected word line during a second time period following the first time period (Fig. 18 where it illustrates the voltage Vr2 applied to the selected word line during the second time period (t3)),
and selectively applying the on-voltage to the second ground select line based on characteristics of the selected word line during the second time period (Fig. 18 where it illustrates the pulse on the unselected ground select line at the start of the 2nd sense/read period. It is noted that this limitation appears directed toward Fig. 15 and para. 129-132 of the instant application and specifically, where it states: " FIG. 15, after the first sensing period ends, a pre-pulse may be applied to the ground select line GSL2 at a sixth time point t16." The time point t16 is the start of the 2nd sensing period and the pulse at that time are both analogous to Seo. Regarding the basis characteristic of the selected word line, it is observed that there is no structure claimed nor means disclosed in the instant application which indicates or determines that characteristic or if it may even be predetermined during manufacturing or test of the device and thus a static condition. Further, while the specification conveys various examples of what the characteristic may be, there are no specific metes and bounds to define the full scope of this feature. Therefore, the limitation for this claim will be understood using the broadest reasonable interpretation to mean that the selected word line exists and exhibits some static material property.).
Regarding claim 18, Joe, Kim, Seo and Joo disclose the limitations of claim 17.
As applied, Seo further discloses 18 wherein
the characteristics of the selected word line include at least one of (As noted above, the claimed characteristic is taken to mean exhibiting some static material property.)
a stacking position of the selected word line among the plurality of word lines (para. 6; "a non-volatile memory device including: a memory cell array which includes", "a first memory cell and a first ground select transistor stacked sequentially in a first direction", "wherein a first word line is connected to the first memory cell". It is noted that whatever memory cell is selected, it would exist, and it's word line would necessarily exibit the static material property of a position within the stack),
a width of a channel hole connected to the selected word line,
a distance between the channel and an end of the selected word line,
a thickness of an insulating layer between the selected word line and the channel,
or a voltage level applied to the selected word line during a sensing period.
Regarding claim 19, Joe, Kim, Seo and Joo disclose the limitations of claim 16.
As applied, Seo further discloses further comprising:
applying the on-voltage to the string select lines while applying the on-voltage to the second ground select line (Fig. 6 where it illustrates string select lines sel_DSL at Von while ground select line sel_SSL goes to Vssl at time T7).
Regarding claim 20, Joe, Kim, Seo and Joo disclose the limitations of claim 19.
As applied, Seo further discloses further comprising:
maintaining a voltage applied to a string select line connected to the at least one second unselected string at an off-voltage (Fig. 6 where it illustrates string select lines unsel_DSL maintained at Voff from time T3 through at least T8).
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive because, while the applicant's contention on pg. 4 and 5 of Remarks that the amendments to independent claim 1 which narrowed the claim scope are not disclosed by the previously applied references, new facts of the applied prior art combined with the new features which required further consideration and search resulting in new references remains unpatentable under a new ground of rejection.
Applicant contends on pg. 5 of Remarks that since independent claims 10 and 16 are amended to include similar subject matter as claim 1 and are thus allowable for the same or similar reasons. As stated above, claim 1 remains rejected and given similar consideration, claims 10 and 16 likewise remain rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825