DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, including claims 1-10 and 20, in the reply filed on 2/24/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (PG Pub. No. US 2020/0105735 A1).
Regarding claim 1, Park teaches a semiconductor device (¶ 0038: 100), comprising:
a stack structure (fig. 4 among others) comprising alternative conductive layers (¶ 0040: 230) and dielectric layers (¶ 0040: 220); and
a gate line structure (¶ 0040: separation regions SS and/or SR) extending vertically through the stack structure (¶ 0040: SS/SR extend through stacked structure of 230/220) and laterally along a first lateral direction to divide the stack structure into memory fingers (fig. 3: SS/SR laterally divides stack into horizontal finger regions), the gate line structure comprising:
gate line slit structure segments (¶ 0040: SS/SR) aligned along the first lateral direction (fig. 3: SS/SR aligned along X-direction), and
at least one first dummy contact structure (¶ 0056 & fig. 4: 260, extending between layers 230 and electrically isolated from bonding pads 280) located between adjacent gate line slit structure segments in the first lateral direction (figs. 3-4: at least one isolated 260 located between SS/SR portions).
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Regarding claim 2, Park teaches the semiconductor device of claim 1, wherein:
the at least one first dummy contact structure is located in an array region or in a staircase region (¶ 0045 & figs. 3-4: dummy contacts 260 located in staircase structure in region CTR).
Regarding claim 3, Park teaches the semiconductor device of claim 2, wherein:
there are a plurality of first dummy contact structures located between adjacent two gate line slit structure segments along the first lateral direction (fig. 3: plurality of 260 between slit structures SS and/or SR).
Regarding claim 4, Park teaches the semiconductor device of claim 3, further comprising:
second dummy contact structures in the staircase region (fig. 3: second contact structures 260 electrically isolated from bit lines 270a,
wherein a first distance between adjacent first dummy contact structures is less than a second distance between adjacent second dummy structures (fig. 3: distance between adjacent first dummy contact structures less than distance between adjacent second dummy structures).
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Regarding claim 5, Park teaches the semiconductor device of claim 4, wherein:
each of the first dummy contact structures and the second dummy contact structures comprises a via structure insulated from the conductive layers of the stack structure by a spacer layer (fig. 4: first dummy contacts 260 include via portion insulated from at least layers 237 & 238 by a portion of insulating layer 290); and
a thickness of the spacer layer of the first dummy contact structure is substantially equal to a thickness of the spacer layer of the second dummy contact structure (fig. 4: thickness of 290 substantially equal for each dummy contact).
Regarding claim 6, Park teaches the semiconductor device of claim 4, further comprising:
gate line contact structures (contacts 260 electrically and/or physically connected to 270a and 230) extending vertically in the staircase region (fig. 4: 260 extend vertically in staircase structure of region CTR).
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Regarding claim 7, Park teaches the semiconductor device of claim 6, wherein:
each gate line slit structure segment comprises a wall structure laterally extending in the first lateral direction (¶ 0049 & fig. 3: SS/SR include an insulating wall structure extending in X-direction) and insulated from the conductive layers of the stack structure (implicit, since SS/SR include insulating material, they are inherently insulated from 230); and
each gate line contact structure comprises a conductive via (¶ 0040: conductive plugs 262) and is electrically connected to a corresponding conductive layer of the stack structure (see annotated fig. 4 above: each 262 electrically connected to corresponding layer of 230).
Regarding claim 8, Park teaches the semiconductor device of claim 7, wherein:
the conductive via is in contact with a landing conductive layer on the corresponding conductive layer, and is insulated from other conductive layers below the corresponding conductive layer (fig. 4: 262 electrically contacts landing portion of corresponding 230 layer, and isolated from underlying 230 layers by layers 220).
Regarding claim 9, Park teaches the semiconductor device of claim 1, wherein:
a width of the gate line slit structure segment in a second lateral direction perpendicular to the first lateral direction is substantially equal to a width of the first dummy contact structure in the second lateral direction (fig. 3: width of SR substantially equal in width to 260 in Y-axis direction).
Regarding claim 10, Park teaches the semiconductor device of claim 6, further comprising: channel structures (¶ 0040: CH) each vertically extending in an array region of the stack structure (fig. 4: CH structures vertically extend in array region CAR of 230/2230 stack).
Regarding claim 20, Park teaches a memory device (¶ 0038: 100), comprising:
a stack structure comprising alternative conductive layers and dielectric layers (fig. 4 among others) comprising alternative conductive layers (¶ 0040: 230) and dielectric layers (¶ 0040: 220);
channel structures (¶ 0040: CH) each vertically extending in an array region of the stack structure (¶ 0041 & fig. 4: CH vertically extends in array region CAR of 230/220 stack);
a gate line structure (¶ 0040: separation regions SS and/or SR) extending vertically through the stack structure (¶ 0040: SS/SR extend through stacked structure of 230/220) and laterally along a first lateral direction to divide the stack structure into memory fingers (fig. 3: SS/SR laterally divides stack into horizontal finger regions), the gate line structure comprising:
gate line slit structure segments (¶ 0040: SS/SR) aligned along the first lateral direction (fig. 3: SS/SR aligned along X-direction), and
first dummy contact structures (fig. 4: contacts 260 electrically isolated from bit lines 270a) aligned close to each other along the first lateral direction (fig. 4: dummy contacts aligned close to each other along X-direction) and located between the gate line slit structure segments in the first lateral direction (fig. 3: at least one dummy contact located between SS/SR in X-direction);
second dummy contact structures aligned discrete with each other and located in a staircase region of the stack structure (figs. 3-4: additional dummy contacts discretely located in staircase structure of CTR region); and
gate line contact structures (260 electrically connected to 270a and 230) extending vertically in the staircase region of the stack structure (fig. 4: 260 connected to 270a and 230 extend vertically in staircase structure of CTR region).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tang (PG Pub. No. US 2022/0028440 A1) teaches a semiconductor device (500), comprising:
a stack structure comprising alternative conductive layers (454) and dielectric layers (456); and
a gate line structure (216) extending vertically through the stack structure (fig. 3) and laterally along a first lateral direction to divide the stack structure into memory fingers (¶ 0061, fig. 2: 216 divides stack into fingers 218), the gate line structure comprising:
gate line slit structure segments (¶ 216) aligned along the first lateral direction (fig. 5), and
at least one first dummy contact structure (222) located between adjacent gate line slit structure segments (fig. 2) in the first lateral direction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818