DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Pursuant to the election of invention I without traverse on February 24, 2026, nonelected claims 11-19 are withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 20 recite “a gate line slit structure extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory blocks”. In the summary, which repeats the claim language, this is also stated ([0006]). However, detailed description states that “[a] gate line slit (GLS) structure 530 can be formed in each slit to divide the memory array into multiple memory fingers 540.” [0095]. The illustrated sections of memory 540 are called “fingers” in the specification, and they appear to be what are called fingers or sub-blocks in the art. There does not appear to be any disclosure of blocks being divided by the claimed gate line slits. Thus there is a discrepancy between the claims and the specification, which results in uncertainty as to the claim scope, as the claims are to be interpreted in light of the specification. For present purposes, the examiner will interpret the claimed dividing into blocks as dividing into blocks or dividing into fingers.
The remaining claims are rejected based on their dependencies.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s).
“a gate line slit structure extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory blocks”
The conductive landing layer.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Zhang, US 2021/0193676 A1.
Claim 1: Zhang discloses
a stack structure comprising an array region (402) and a contact region (404);
and a gate line slit structure (426, 428) extending vertically through the stack structure and laterally along a first lateral direction (horizontal, FIG. 4A) to divide the stack structure into memory blocks, the gate line slit structure comprising:
a first dummy channel structure (414) located at a boundary between the array region and the contact region,
a first gate line slit segment extending laterally from the first dummy channel structure into the array region,
and a second gate line slit segment extending laterally from the first dummy channel structure into the contact region.
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Claim 2: channel structures (410) each vertically extending through the stack structure and located in the array region; and second dummy channel structures (e.g, structure pointed to by number 414) each vertically extending through the stack structure and located in the contact region (FIG. 4A).
Claim 3: the stack structure in the array region comprises conductive layers and first dielectric layers alternatively stacked in a vertical direction (“a stack of word line layers and insulating layers” [0034]); and the stack structure in the contact region comprises: a first contact portion (top finger, FIG. 4A) adjacent to the second gate line slit segment and comprising the conductive layers and the first dielectric layers alternatively stacked in the vertical direction, and a second contact portion (second from top finger, FIG. 4A) separated from the second gate line slit segment by the first contact portion, and comprising first dielectric layers and second dielectric layers alternatively stacked in the vertical direction. Zhang discloses that “The slit structures can have a trench profile, and extend from the substrate and extend through the stack 600.” [0042]. Thus they separate the first and second contact portions 410.
Claim 4: the second dummy channel structures (414) are each vertically extending through the first contact portion (top finger of FIG. 4A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Kim, US 2022/0375862 A1. Zhang does not disclose that a first width of the first dummy channel structure along the first lateral direction is greater than a second width of the first dummy channel structure along a second lateral direction perpendicular to the first lateral direction. However, this is disclosed by Kim, FIG. 7E, which discloses a first width of a first dummy channel structure (150De) along the first lateral direction (horizontal) is greater than a second width of the first dummy channel structure along a second lateral direction (vertical) perpendicular to the first lateral direction. It would have been obvious to have been obvious to have used such a structure in order to improve the productivity of the device ([0117]).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Russo, US 2022/0102378 A1.
Claim 6: Zhang lists the elements of each channel structure, which contains many of the elements recited in claim 6. “Each of the channel structures can further include a channel layer, a tunneling layer that surrounds the channel layer, a charge trapping layer that surrounds the tunneling layer, and a barrier layer that surrounds the charge trapping layer and further is in direct contact to the word line layers. In some embodiments, a high-K layer, such as HfO2 or AlO, can be disposed between the word line layers and the barrier layer.” [0041]. The tunneling layer is commonly made of oxide, the charge trapping layer is commonly made of nitride, and oxide can be used for such barrier layers. Channel layers are semiconductor layers. See also Russo discloses a channel structure comprises a high-k layer (135), a first oxide layer (137, first oxide, [0086], FIG. 5), a nitride layer (124, [0064]), a second oxide layer (137, second oxide, [0086]), a semiconductor layer (142), and a filling structure (551). “Each of the channel structures can further include a channel layer, a tunneling layer that surrounds the channel layer, a charge trapping layer that surrounds the tunneling layer, and a barrier layer that surrounds the charge trapping layer and further is in direct contact to the word line layers. In some embodiments, a high-K layer, such as HfO2 or AlO, can be disposed between the word line layers and the barrier layer.” [0041]. It was common in the art to make the dummy channels in the same process as the regular channels to simplify processing, and thus it would have been obvious to have had the channels of Russo as channels and dummy channels in Zhang as known in the art.
Claim 7: the first dummy channel structure of Zhang in view of Russo comprises an oxide structure (137) and semiconductor (441) laterally surrounded by the oxide structure. The semiconductor layer 441 can be arbitrarily divided into segments, as claim 7 does not recite that they are discontinuous segments.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Shin, US 2019/0027490 A1. Zhang does not disclose that each of the first gate line slit segment and the second gate line slit segment comprises a wall structure laterally extending in the first lateral direction and insulated from the conductive layers. However, this was known in the art and common. See e.g. Sun, which discloses that “an insulating material is deposited in the cut slits” (col. 3 ll24-25). It would have been obvious to have such an insulating fill in order to isolate the fingers. The filled slit would have a wall-shaped structure.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Yun, US 2018/0083030 A1. Zhang does not disclose the details of the connection structure. However, those in the art would have expected contacts connecting to the gate layers, and for it to be surrounded by insulating layers above the stairstep structure in the connection area, as in Yun FIG. 6. It would have been obvious to have had such an arrangement as common and expected.
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Claim 10: in Zhang in view of Yun, the gate line contact structures each comprise a conductive landing layer (the end of the gate line 120) in the second contact portion and laterally in contact with a corresponding conductive layer (120); and a conductive via (CNT) vertically through the second dielectric layers and first dielectric layers above the conductive landing layer and in contact with the conductive landing layer. As no distinction is made, structurally, materially, or otherwise, between conductive layer and the landing layer, the landing layer can be considered the end of the conductive layer 120.
Claim 20: Zhang in view of Yun discloses:
a stack structure comprising:
a first conductive/dielectric stack in an array region (Zhang 402),
(“a stack of word line layers and insulating layers” [0034])
a second conductive/dielectric stack in a contact region (404),
and a dielectric stack (Yun, 170) in the contact region;
a gate line slit structure (426, 428) extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory blocks, the gate line slit structure comprising:
a first dummy channel structure (414) located at a boundary between the array region and the contact region,
a first gate line slit segment extending laterally from the first dummy channel structure into the array region,
and a second gate line slit segment extending laterally from the first dummy channel structure into the contact region;
channel structures (410) each extending vertically through the first conductive/dielectric stack;
second dummy channel structures (e.g, structure pointed to by number 414) each extending vertically through the second conductive/dielectric stack and adjacent to the second gate line slit segment;
and gate line contact (CNT) structures each extending vertically in the dielectric stack and laterally in contact with corresponding conductive layers of the second conductive/dielectric stack (Yun FIG. 6).
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Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, if the 112 rejection is resolved. Did not find a dummy channel with an oxide structure having a convex sidewall on the first side and a concave sidewall surface on the second side, with all the other features of claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
Prosecution Insights