DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I: claims 1-9 and 20 in the reply filed on 05/28/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “each channel structure comprises a first oxide layer, a nitride layer, a second oxide layer, a semiconductor layer, and a filling structure; and each dummy channel structure comprises an oxide structure having convex sidewall surfaces facing adjacent gate line slit structure segments, and at least one semiconductor layer and a filling structure embedded in the oxide structure” (as recited claim 6) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “conductive via is in contact with a landing conductive layer on the corresponding conductive layer, and insulated from other conductive layers below the corresponding conductive layer” (as recited claim 9) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (US 2021/0193676; hereinafter Zhang ‘676)
Regarding claim 1, Zhang ‘676 teaches a semiconductor device (refer to item 100; see fig. 1A-1B), comprising:
a stack structure comprising alternative conductive layers and dielectric layers (see par. 34); and
a gate line structure (separation regions 418/420/422/424/426/428) extending vertically through the stack structure (see par. 42) and laterally along a first lateral direction to divide the stack structure into memory blocks (fig. 4A), the gate line structure comprising:
gate line slit structure segments (refer to 418/420/422/424/426/428) aligned along the first lateral direction (see fig. 4A: refer to x-axis), and
at least one dummy channel structures (par. 40 and refer to item 414 in fig. 4A) located between the gate line slit structure segments (refer to first gate slit segment and a second gate slit segment as labelled below in fig. 4A) in the first lateral direction (refer to x-axis).
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Regarding claim 2, Zhang ‘676 teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 4A of Zhang ‘676 teaches gate line contact structures (412) and dummy contact structures (414), each extending vertically in a staircase region of the stack structure (see par. 40 and 42).
Regarding claim 3, Zhang ‘676 teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 4A of Zhang teaches channel structures (410) each vertically extending in an array region of the stack structure (see par. 41).
Regarding claim 8, Zhang ‘676 teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Zhang ‘676 teaches each gate line contact structure (412) comprises a conductive via and is electrically connected to a corresponding conductive layer of the stack structure (see par. 40).
Regarding claim 20, Zhang ‘676 teaches a semiconductor device fig. 4A, comprising:
a stack structure comprising alternative conductive layers and dielectric layers (see par. 34); and
a gate line structure separation regions (418/420/422/424/426/428) extending vertically through the stack structure and laterally along a first lateral direction to divide the stack structure into memory blocks (See par. 42 and fig. 4A), the gate line structure comprising:
gate line slit structure segments (refer to 418/420/422/424/426/428) aligned along the first lateral direction, and
dummy channel structures (refer to 414; see par. 40) aligned close to each other along the first lateral direction and located between the gate line slit structure segments in the first lateral direction;
gate line contact structures (412) and dummy contact structures (414), each extending vertically in a staircase region of the stack structure (see par. 40 and 42); and
channel structures (410) each vertically extending in an array region of the stack structure.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang ‘676 as applied to claim 1 above, and further in view of Zhang (US 20220085056; hereafter Zhang ‘056).
Regarding claim 4, Zhang ‘676 teaches all the limitations of the claimed invention for the same reasons as set forth above except for each gate line slit structure segment comprises a wall structure laterally extending in the first lateral direction and insulated from the conductive layers of the stack structure.
Zhang ‘056 teaches the same field of an endeavor wherein each gate line slit structure segment comprises a wall structure laterally extending in the first lateral direction and insulated from the conductive layers of the stack structure (see par. 43).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include each gate line slit structure segment comprises a wall structure laterally extending in the first lateral direction and insulated from the conductive layers of the stack structure by Zhang ‘056 in the teaching of Zhang ‘676 so that it protect eh first and second dielectric layers (see par. 43).
Regarding claim 5, Zhang ‘676 and Zhang ‘056 teach all the limitations of the claimed invention for the same reasons as set forth above. Besides, Zhang ‘676 teaches each of the channel structures and the dummy channel structures comprises a high-k layer, a first oxide layer, a nitride layer, a second oxide layer, a semiconductor layer, and a filling structure (see par. 41).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang ‘676 as applied to claim 1 above, and further in view of Kim (US 20220375862).
Regarding claim 7, Zhang ‘676 teaches all the limitations of the claimed invention for the same reasons as set forth above except for a first width of the dummy channel structure along the first lateral direction is greater than a second width of the dummy channel structure along a second lateral direction perpendicular to the first lateral direction.
Kim teaches the same field of an endeavor wherein a first width of the dummy channel structure (refer to elliptical shapes dummy channel structures 150Ee) along the first lateral direction (refer to horizontal direction) is greater than a second width of the dummy channel structure along a second lateral direction (refer to vertical direction) perpendicular to the first lateral direction (see fig. 7E).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a first width of the dummy channel structure along the first lateral direction is greater than a second width of the dummy channel structure along a second lateral direction perpendicular to the first lateral direction as taught by Kim in the teaching of Zhang ‘676 in order to provide an alternative of making product.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang ‘676 as applied to claim 1 above, and further in view of Han (US 2021/0050368).
Regarding claim 9, Zhang teaches all the limitations of the claimed invention for the same reasons as set forth above except for the conductive via is in contact with a landing conductive layer on the corresponding conductive layer, and insulated from other conductive layers below the corresponding conductive layer.
Han teaches the same field of an endeavor wherein the conductive via (145,155,165) is in contact with a landing conductive layer on the corresponding conductive layer, and insulated from other conductive layers below the corresponding conductive layer (see fig. 1A and 1B; see par. 42).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the conductive via is in contact with a landing conductive layer on the corresponding conductive layer, and insulated from other conductive layers below the corresponding conductive layer as taught by Hang in the teaching of Zhang in order to connect driving circuitry, such as word line driving circuitry, ground select driving circuitry, string select driving circuitry, and the like in the periphery circuitry to the respective gates of the transistors in the stack (see par. 42).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or “each channel structure comprises a first oxide layer, a nitride layer, a second oxide layer, a semiconductor layer, and a filling structure; and each dummy channel structure comprises an oxide structure having convex sidewall surfaces facing adjacent gate line slit structure segments, and at least one semiconductor layer and a filling structure embedded in the oxide structure.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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