Prosecution Insights
Last updated: July 17, 2026
Application No. 18/516,159

VERTICAL GATE DRAM DEVICE

Non-Final OA §103
Filed
Nov 21, 2023
Priority
Nov 09, 2023 — CN 202311493928.3
Examiner
MALEK, MALIHEH
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co., Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
477 granted / 602 resolved
+11.2% vs TC avg
Minimal +4% lift
Without
With
+3.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
19 currently pending
Career history
627
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
85.2%
+45.2% vs TC avg
§102
8.2%
-31.8% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 602 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to the election filed on 05/08/2026. Group II, claims 10-20 have been elected without traverse. Currently, claims 10-20 are pending, and claims 1-9 have been withdrawn from further consideration. DETAILED ACTION Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shao et al. (Pub. No. US 2024/0274684 A1) in view of Zhu (Pub. No. US 2019/0279980 A1). Regarding claim 10 or 16, Shao discloses a memory system ([0003]), comprising: a semiconductor device configured to store data, and comprising: at least one vertical pillar 32 ([0097]), the at least one vertical pillar has a first end and a second end opposite to the first end (Fig. 29); at least one gate line 100 (Fig. 28 and [0111]) on a gate dielectric layer 101 ([0108]) formed on sidewalls of the at least one vertical pillar; a first p-type region 321 ([0098]) at the first end of the at least one vertical pillar; a storage unit 150 ([0120]) connects with the first p-type region; a second p-type region 323 ([0098]) at the second end of the at least one vertical pillar; and a bit line 80 ([0103]) in connection with the second p-type region at the second end of the at least one vertical pillar (Figs. 29-30); and a memory controller coupled to the semiconductor device and configured to control the semiconductor device through the at least one gate line and the bit line ([0003], [0037]-[0038]). Shao does not specifically show the second p-type region comprises at least p-type silicon germanium (SiGe). However, in the same field of endeavor, Zhu discloses a semiconductor device, comprising: at least one vertical pillar, the at least one vertical pillar has a first end and a second end opposite to the first end (Figs. 27, 33); a gate dielectric layer 1015 ([0074]) formed on sidewalls of the at least one vertical pillar; a first p-type region 1005p ([0049]) at the first end of the at least one vertical pillar; a storage unit 1101/1203 ([0086]) connects with the first p-type region; a second p-type region 1031p ([0089]) at the second end of the at least one vertical pillar, the second p-type region comprises at least p-type silicon germanium (SiGe) that has a greater lattice constant than Si, creates etch selectivity ([0045]) and enhances carrier mobility. Therefore, given the teachings of Zhu, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Shao in view of Zhu by employing the SiGe p-type region. Regarding claims 11 and 19, Shao in view of Zhu teaches the semiconductor device of claim 10, wherein the first p-type region has a dopant concentration higher than 1019 atoms/cm3 (Zhu: [0098]). Regarding claims 12 and 20, Shao in view of Zhu teaches the semiconductor device of claim 10, wherein the second p-type region has a dopant concentration higher than 1019 atoms/cm3 (Zhu: [0098]). Regarding claims 13 and 17, Shao in view of Zhu teaches the semiconductor device of claim 10, wherein the gate line and the bit line are formed so that they are perpendicular to each other (Shao: Fig. 29 and [0005], [0085]). Regarding claim 14, Shao in view of Zhu teaches the semiconductor device of claim 10, wherein the gate line is encapsulated by an oxide layer (Shao: [0094]; The use of oxide as an isolation or a protective layer is well-known in the art.). Regarding claims 15 and 18, Shao in view of Zhu teaches the semiconductor device of claim 10, wherein the storage unit is a capacitor (Shao: [0120]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. June 24, 2026 /MALIHEH MALEK/Primary Examiner, Art Unit 2813
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Prosecution Timeline

Nov 21, 2023
Application Filed
Jun 29, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
83%
With Interview (+3.6%)
2y 10m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 602 resolved cases by this examiner. Grant probability derived from career allowance rate.

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