DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 11-17 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (2013/0200528).
Regarding claims 1, 3, 11 and 20, Lin (Fig. 31) discloses a semiconductor package 860 comprising: a first redistribution wiring layer 782 having a first region (the region between two # 776) and a second region (the # 776 on the left and the # 776 on the right) surrounding the first region ([0245]), the first redistribution wiring layer 782 including a plurality of first redistribution wirings 740 ([0229]); a semiconductor chip 276 disposed on the first region of the first redistribution wiring layer 740 and electrically connected to the plurality of first redistribution wirings 740 ([0245]); a sealing member (696, 764) on the first redistribution wiring layer 782 ([0219]), the sealing member (696, 764) covering the semiconductor chip 276 on the first redistribution wiring layer 740 ([0219] and [0246]); a plurality of vertical conductive wires 776 penetrating the sealing member (696, 764) on the second region of the first redistribution wiring layer 740 and electrically connected to the plurality of first redistribution wirings 740 ([0241]); a second redistribution wiring layer 786 disposed on the sealing member (696, 764) ([0247]), the second redistribution wiring layer 786 including a plurality of second redistribution wirings 740 electrically connected to the plurality of vertical conductive wires 776; and a plurality of bonding pads 720/722 provided on an upper surface of the first redistribution wiring layer 782 ([0220]) or a lower surface of the second redistribution wiring layer 786, wherein each of the plurality of bonding pads 722 has a concavo-convex pattern in a bonding surface thereof ([0220]), and the concavo-convex pattern has a plurality of grooves filled with a metal of the corresponding vertical conductive wire 776 (see Fig. 31, [0280]).
Regarding claims 2 and 12, Lin (Fig. 31) discloses wherein each of the plurality of bonding pads 722 includes copper ([0242]), and each of the plurality of vertical conductive wires 776 includes at least one of gold, silver and copper ([0280]).
Regarding claims 4 and 13, Lin (Fig. 31) discloses wherein the concavo-convex pattern is provided in the surface of the bonding pad 722 and a side surface of the bonding pad 722.
Regarding claims 5 and 14, Lin (Fig. 31) discloses further comprising: a plating pattern provided on the concavo-convex pattern ([0241]). It is note that the process limitation (a plating pattern) would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced. In re Thorpe, 227 USPQ 964 (Fed. Cir. 1985).
Regarding claims 6 and 15, Lin (Fig. 31) discloses wherein the plating pattern 776 includes at least one of nickel and gold ([0280]).
Regarding claims 7 and 16, Lin (Fig. 31) discloses wherein the concavo-convex pattern includes an embossed plating pattern formed on the surface of the bonding pad 722 (see Fig. 26m).
Regarding claims 8 and 17, Lin (Fig. 31) discloses wherein the vertical conductive wire 776 covers a side surface of the bonding pad 722.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-10 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (2013/0200528) in view of Jung et al. (2022/0130786).
Regarding claims 10 and 19, Lin discloses all the claimed limitations of the invention except for further comprising: a second package disposed on the second redistribution wiring layer, wherein the second package includes a package substrate and at least one second semiconductor chip stacked on the package substrate.
However, Jung (Fig. 31) discloses a second package 600 disposed on the second redistribution wiring layer 350, wherein the second package 600 includes a package substrate 610 and at least one second semiconductor chip 620/630 stacked on the package substrate 610 (see Figs. 31, [0139]) in order to provide the device designed for an intended purpose. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the device of Lin by a second package disposed on the second redistribution wiring layer, wherein the second package includes a package substrate and at least one second semiconductor chip stacked on the package substrate in order to complete the semiconductor device for an intended purpose, as taught by Jung (Fig. 31, [0139]).
Regarding claim 9, Lin (Fig. 31) discloses wherein the bonding pad 722 has a diameter of 1 µm to 500 µm ([0247]), and the vertical conductive wire 776 has a maximum diameter of 50 µm to 150 µm ([0238]).
Lin does not tech the vertical conductive wire has a maximum diameter of 2.5 µm to 100 µm. However, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardner v. TEC Systems, Inc., 725 F. 2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to form the device as claimed above, because the dimensions can be optimized during routine experimentation, depending upon the device in a particular application.
Regarding claim 18, Lin discloses all the claimed limitations of the invention except for the semiconductor chip is mounted on the first redistribution wiring layer via conductive bumps.
However, Lin in different embodiment of Fig. 6 discloses wherein the semiconductor chip 112 is mounted on the first redistribution wiring layer 156 via conductive bumps 114 for depending upon the device in a particular application. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to modify the embodiment in Fig. 6 of Lin’s device by forming the semiconductor chip is mounted on the first redistribution wiring layer via conductive bumps for depending upon the device in a particular application, as taught by the different embodiment in Fig. 6 of Lin.
Conclusion
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/THERESA T DOAN/ Primary Examiner, Art Unit 2814