DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2, Embodiment II, Figs. 2A-2F, claims 1, 3-12 and 21-28, in the reply filed on March 30, 2026 is acknowledged. Claims 13-20 have been cancelled by the Applicant. Action on the merits is as follows:
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipate by JangJian et al. (JangJian) (US 2016/0111325 A1).
In regard to claim 21, JangJian (Figs. 2-14 and associated text) discloses a method, comprising: forming a first intermetal dielectric layer (items 24 plus 28 or 24 plus 28 plus 26) above a plurality of transistors (item 22, paragraph 15); forming a plurality of metal lines (items 32 on left and right) on the first intermetal dielectric layer (items 24 plus 28 or 24 plus 28 plus 26); depositing a sealing layer (items 38, 40a, 40b, 40c, 38 plus 40a, 38 plus 40a plus 40b or 38 plus 40a plus 40b plus 40c) on top surfaces of the metal lines (items 32 on left and right); and depositing a second intermetal dielectric layer (items 30 plus 42) on the on the first intermetal dielectric layer (items 24 plus 28 or 24 plus 28 plus 26) and on the metal lines (items 32 on left and right), wherein the second intermetal dielectric layer (items 30 plus 42) includes a first intermetal dielectric sublayer (item 30) having a top surface that is coplanar with the top surface of the sealing layer (items 38, 40a, 40b, 40c, 38 plus 40a, 38 plus 40a plus 40b or 38 plus 40a plus 40b plus 40c), wherein the second intermetal dielectric layer (items 30 plus 42) includes a second intermetal dielectric sublayer (item 42) on the first intermetal dielectric sublayer (item 30) and having a planar top surface.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5-12 and 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over JangJian et al. (JangJian) (US 2016/0111325 A1) in view of Lisker et al. (Lisker) “Combining SiGe BiCMOS and InP Processing in an On-top of Chip Integration Approach”.
In regard to claim 1, JangJian (Figs. 2-14 and associated text) discloses a method, comprising: forming a transistor (item 22, paragraph 15); forming a first intermetal dielectric layer (items 24 plus 28) above the transistor (item 22); forming a plurality of metal lines (items 32 on left and right) with a sealing layer (items 38, 40a, 40b, 40c, 38 plus 40a, 38 plus 40a plus 40b or 38 plus 40a plus 40b plus 40c) covering at least a top of each metal line (items 32 on left and right); forming a first intermetal dielectric sub-layer (item 30) between the metal lines (items 32 on left and right) and on the sealing (items 38, 40a, 40b, 40c, 38 plus 40a, 38 plus 40a plus 40b or 38 plus 40a plus 40b plus 40c) above the metal lines (items 32 on left and right), but does not specifically disclose performing a CMP process on the first intermetal dielectric sub-layer including using the sealing layer as an etch stop layer to stop the CMP process.
Lisker (Fig. 1 and associated text) discloses performing a CMP process on the first intermetal dielectric sub-layer (shown but not labeled) including using the sealing layer (SiN) as an etch stop layer (SiN) to stop the CMP process.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Lisker for the purpose of improving process flow which helps achieve nearly zero (< 100nm) step height, which also assist with wafer bonding processes.
In regard to claim 3, JangJian (Figs. 2-14 and associated text) discloses wherein forming the metal lines (items 32 on left and right) and the sealing layer (item 38) includes: forming a metal stack (items 32 on left and right) on the first intermetal dielectric layer (items 24 plus 28); forming the sealing layer (items 38, 40a, 40b, 40c, 38 plus 40a, 38 plus 40a plus 40b or 38 plus 40a plus 40b plus 40c) on a top of the metal stack (items 32 on left and right); and patterning the sealing layer (items 38, 40a, 40b, 40c, 38 plus 40a, 38 plus 40a plus 40b or 38 plus 40a plus 40b plus 40c) and the metal stack (items 32 on left and right) to form the plurality of metal lines (items 32 on left and right) with the sealing layer (items 38, 40a, 40b, 40c, 38 plus 40a, 38 plus 40a plus 40b or 38 plus 40a plus 40b plus 40c) on the top of the metal lines (items 32 on left and right).
In regard to claim 5, JangJian as modified by Lisker does not specifically disclose wherein the first intermetal dielectric layer is silicon oxide.
It would have been obvious to modify the invention to include a first intermetal dielectric layer being silicon oxide, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regard to claim 6, JangJian (Figs. 2-14 and associated text) discloses depositing a second intermetal dielectric sub-layer (item 42) on the first intermetal dielectric sub-layer (item 30).
In regard to claim 7, JangJian (Figs. 2-14 and associated text) discloses wherein the second intermetal dielectric sub-layer (item 42) has a top surface that is substantially planar without CMP.
In regard to claim 8, JangJian (Figs. 2-14 and associated text) discloses wherein the first intermetal dielectric sub-layer (item 30) and the second intermetal dielectric sub-layer (item 42) collectively form a second intermetal dielectric layer (items 30 plus 42).
In regard to claim 9, JangJian (Figs. 2-14 and associated text) discloses comprising: exposing a top surface of one of the metal lines (items 32 on left and right) by forming a trench (items 44, 46 or 44 plus 46) in the second intermetal dielectric sub-layer (item 42); and forming a conductive via (items 48, 50 or 48 plus 50) in the trench (items 44, 46 or 44 plus 46) in contact with the top surface of the metal line (items 32 on left or right).
In regard to claim 10, JangJian (Figs. 2-14 and associated text) discloses wherein a first distance between a top surface of a first one of the metal lines (items 32 on left or right) and a top surface of the second intermetal dielectric sub-layer (item 42) is substantially the same as a distance between a top surface of a second one of the metal lines (items 32 on left or right) and the top surface of the second intermetal dielectric sub-layer center (item 42), wherein the first one of the metal lines (items 32 on left or right) is in an integrated circuit near a center of a wafer (item 20), wherein the second one of the metal lines (items 32 on left or right) in a second integrated circuit near an edge of the wafer (item 20).
In regard to claim 11, JangJian (Figs. 2-14 and associated text) as modified by Lisker (Fig. 1 and associated text) discloses wherein the sealing layer (items 38, 40a, 40b, 40c, 38 plus 40a, 38 plus 40a plus 40b or 38 plus 40a plus 40b plus 40c, JangJian, not labeled but shown, Lisker) is made of one of: silicon nitride, silicon carbonitride (SiCN), aluminum nitride (AlN), alumina (Al.sub.2O.sub.3), hafnium oxide (HfO.sub.2), Hafnium alumino-oxide (Hf.sub.xAl.sub.yO.sub.z) (paragraph 23, JangJian, comprise nitrogen, metal carbo-nitride).
It would have been obvious to modify the invention to include a sealing layer made of one of: silicon nitride, silicon carbonitride (SiCN), aluminum nitride (AlN), alumina (Al.sub.2O.sub.3), hafnium oxide (HfO.sub.2) or Hafnium alumino-oxide (Hf.sub.xAl.sub.yO.sub.z), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regard to claim 12, JangJian (Figs. 2-14 and associated text) as modified by Lisker does not specifically disclose the sealing layer has a thickness greater than or equal to 50 nm and less than or equal to 500 nm.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a thickness greater than or equal to 50 nm and less than or equal to 500 nm, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regard to claim 22, JangJian (Figs. 2-14 and associated text) discloses depositing a stack of metal layers (items 32 on left and right) on the first intermetal dielectric layer (items 24 plus 28 or 24 plus 26 plus 28); depositing the sealing layer (items 38, 40a, 40b, 40c, 38 plus 40a, 38 plus 40a plus 40b or 38 plus 40a plus 40b plus 40c) on the stack of metal layers (items 32 on left and right), but does not specifically disclose forming a plurality of metal lines by patterning sealing layer (SiN) and the metal layers.
Lisker (Fig. 1 and associated text) discloses forming a metal line (shown but not labeled) by patterning sealing layer(SiN) and the metal layers (Ti/Ti/AlCu/TiN).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Lisker for the purpose of improving process flow which helps achieve nearly zero (< 100nm) step height, and forming metal line.
In regard to claim 23, JangJian (Figs. 2-14 and associated text) discloses wherein the first intermetal dielectric sublayer (item 30) is in contact with sidewalls of the metal lines (items 32 on left and right).
In regard to claim 24, JangJian as modified by Lisker (Fig. 1 and associated text) discloses further comprising performing a CMP process after depositing the first interlevel dielectric sublayer (shown but not labeled), wherein the sealing layer (SiN) on the top surfaces of the metal lines (shown but not labeled) is an etch stop layer for the CMP process.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Lisker for the purpose of improving process flow which helps achieve nearly zero (< 100nm) step height, which also assist with wafer bonding processes.
Claim(s) 4 and 25-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over JangJian et al. (JangJian) (US 2016/0111325 A1) in view of Lisker et al. (Lisker) “Combining SiGe BiCMOS and InP Processing in an On-top of Chip Integration Approach” as applied to claims 1, 3, 5-12 and 22-24 above, and further in view of Achuthan et al. (Atchuthan) (US 6,413,869 B1) as evidenced by Choi et al. (US 2017/0040208 A1) or Fu et al. (Fu) (TW 202139277 A).
In regard to claim 4, JangJian as modified by Lisker (Fig. 1 and associated text) discloses using the sealing layer (SiN) as the etch stop, but does not specifically disclose wherein performing the CMP process includes: performing a first CMP step corresponding to a timed CMP step; and performing a second CMP step after the time CMP step including using the sealing layer as the etch stop, and wherein the first CMP step includes using a first slurry, wherein the second CMP step includes using a second slurry different from the first etch chemistry.
Achuthan (column 5, lines 23-33) wherein performing the CMP process includes: performing a first CMP step corresponding to a timed CMP step; and performing a second CMP step after the time CMP step including using the sealing layer (capping layer, column 2, lines 25-31) as the etch stop, and wherein the first CMP step includes using a first slurry, wherein the second CMP step includes using a second slurry different from the first etch chemistry.
Therefore it would have been obvious to one of ordinary skilled in the art before the effective filing date to incorporate the teachings of Achuthan for the purpose of further etching/polishing/removal.
As evidenced by Choi, the first and second CMP step can be timed CMP steps (Abstract).
As evidenced by Fu, the first and second CMP step can be time CMP steps having a first slurry and a second slurry (Abstract, MODE-FOR-INVENTION).
Therefore it would have been obvious to one of ordinary skilled in the art before the effective filing date to incorporate the teachings of Choi or Fu for the purpose of preventing over-etching/polishing/removal or having the desired etching/polishing/removal of material.
In regard to claim 25, JangJian (Figs. 2-14 and associated text) as modified by Lisker (Fig. 1 and associated text), Achuthan (column 5, lines 23-33) and Choi (Abstract) discloses wherein the CMP process includes a first CMP step with a first etching rate of the first interlevel dielectric sublayer (item 30, JangJian) and a second step with a second etching rate of the first interlevel dielectric sublayer (item 30, JangJian).
In regard to claim 26, JangJian (Figs. 2-14 and associated text) discloses a method, comprising: forming a transistor (item 22, paragraph 15); depositing a first intermetal dielectric layer (items 24 plus 28 or 24 plus 28plus 26) above the transistor (item 22); forming a first metal line (item 32 on the left or right) and a second metal line (item 32 on the left or right) on the first intermetal dielectric layer (items 24 plus 28 or 24 plus 28plus 26), wherein a sealing layer (items 38, 40a, 40b, 40c, 38 plus 40a, 38 plus 40a plus 40b or 38 plus 40a plus 40b plus 40c) is positioned on top surfaces of the first and second metal lines (item 32 on the left and right); depositing a second intermetal dielectric layer (items 30, 42 or 30 plus 42) over the first intermetal dielectric layer (items 24 plus 28 or 24 plus 28plus 26) between the first and second metal lines (item 32 on the left and right) and on the sealing layer (items 38, 40a, 40b, 40c, 38 plus 40a, 38 plus 40a plus 40b or 38 plus 40a plus 40b plus 40c) but does specifically disclose using the sealing layer as an etch stop.
Lisker (Fig. 1 and associated text) discloses using the sealing layer (SiN) as the etch stop. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Lisker for the purpose of improving process flow which helps achieve nearly zero (< 100nm) step height, which also assist with wafer bonding processes.
JangJian as modified by Lisker does not specifically disclose performing a first CMP step on the second intermetal dielectric layer with a first slurry having a first etch chemistry; and performing a second CMP step on the second intermetal dielectric layer with a second slurry having a second etch chemistry different from the first etch chemistry.
Achuthan (column 5, lines 23-33) wherein performing the CMP process includes: performing a first CMP step corresponding to a timed CMP step; and performing a second CMP step after the time CMP step including using the sealing layer (capping layer, column 2, lines 25-31) as the etch stop, and wherein the first CMP step includes using a first slurry, wherein the second CMP step includes using a second slurry different from the first etch chemistry.
Therefore it would have been obvious to one of ordinary skilled in the art before the effective filing date to incorporate the teachings of Achuthan for the purpose of further etching/polishing/removal.
As evidenced by Choi, the first and second CMP step can be timed CMP steps (Abstract).
As evidenced by Fu, the first and second CMP step can be time CMP steps having a first slurry and a second slurry (Abstract, MODE-FOR-INVENTION).
Therefore it would have been obvious to one of ordinary skilled in the art before the effective filing date to incorporate the teachings of Choi or Fu for the purpose of preventing over-etching/polishing/removal or having the desired etching/polishing/removal of material.
In regards to claim 27, JangJian as modified by Lisker, Achuthan and evidence by Choi does not specifically disclose wherein the second intermetal dielectric layer includes silicon oxide.
It would have been obvious to modify the invention to include a second intermetal dielectric layer including silicon oxide, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regard to claim 28, JangJian (Figs. 2-14 and associated text) discloses wherein the second intermetal dielectric layer (items 30, 42 or 30 plus 42) is in contact with sidewalls of the first and second metal lines (item 32 on the left and right).
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 April 7, 2026
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