DETAILED ACTION
This Office action is in response to the application filed 21 November 2023. Claims 1-15 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 14, and 15are rejected under 35 U.S.C. 102(a)(2) as being anticipated by 2024/0055566 A1 to Tae et al. (hereinafter “Tae”).
Regarding independent claim 1, Tae (Figs. 5, 10) discloses a display device, comprising:
a substrate SUB (Fig. 5; ¶ 0092) including an active area DA (¶ 0092) and a non-active area NDA (¶ 0092), the active area including a plurality of sub pixels (¶¶ 0102, 0075);
a first assembly line BNK1/EL1_1 (BNK1 to left of LD1; ¶ 0195) and a second assembly line BNK1/EL2 (BNK1 to right of LD1; ¶ 0195) both disposed in the plurality of sub pixels on the substrate and being separated from each other to form a separated space (Figs. 10, 8 - figures are understood to be a representative portion of the display device);
a light emitting diode LD1 (¶ 0215) disposed in the plurality of sub pixels and disposed on the first assembly line and the second assembly line; and
a capacitor Cst disposed below the first assembly line and the second assembly line, wherein the capacitor is disposed so as to overlap the separated space between the first assembly line and the second assembly line (Fig. 10).
Regarding claim 2, Tae (Fig. 10) discloses the display device according to claim 1, wherein the capacitor Cst is disposed so as to overlap the light emitting diode LD1 (Fig. 10).
Regarding claim 3, Tae (Fig. 10) discloses the display device according to claim 1, wherein a bottom surface of the light emitting diode LD1 overlaps the capacitor Cst in an area between the first assembly line BNK1/EL1_1 (BNK1 to left of LD1) and the second assembly line BNK1/EL2 (BNK1 to right of LD1)(Fig. 10).
Regarding claim 4, Tae (Fig. 10) discloses the display device according to claim 1, wherein the first assembly line BNK1/EL1_1 (BNK1 to left of LD1) and the second assembly line BNK1/EL2 (BNK1 to right of LD1) include a protrusion (portion of El1_1 and portion of EL2 extending toward LD1) protruding toward an area overlapping the light emitting diode LD1, and the protrusion is disposed so as to overlap the capacitor Cst (Fig. 10).
Regarding claim 5, Tae (Fig. 10) discloses the display device according to claim 4, further comprising: a transistor T1 disposed on the substrate SUB; and a light shielding layer BFL (¶ 0179) disposed between the transistor and the substrate (Fig. 10).
Regarding claim 7, Tae (Fig. 10) discloses the display device according to claim 1, further comprising: a plurality of transistors (Figs. 6A-E - transistors T; ¶¶ 0107, 0114) disposed on the substrate in each of the plurality of sub pixels, wherein each of the plurality of sub pixels includes a first area having the plurality of transistors disposed therein, and a second area extended from the first area and having the capacitor Cst disposed therein (Figs, 8, 10 - a “first area” containing the transistors and “second area” containing Cst are defined to meet the recited limitations).
Regarding claim 8, Tae (Fig. 10) discloses the display device according to claim 1, further comprising: a driving transistor T1 (¶ 0180) disposed on the substrate SUB; a pixel electrode CNE2 (¶ 0195) disposed on the light emitting diode LD1 to be electrically connected to the light emitting diode; and a connection electrode EL2 (¶ 0195) connecting the pixel electrode and the driving transistor (Fig. 10 - EL2 connects to DVL/PL2 which is electrically connected to T1).
Regarding claim 9, Tae (Fig. 10) discloses the display device according to claim 8, wherein the light emitting diode LD1 overlaps an area between an area in which the connection electrode EL2 is disposed and an area in which the driving transistor T1 is disposed (Fig. 10).
Regarding claim 14, Tae (Figs. 10, 3A) discloses the display device according to claim 1, wherein the light emitting diode LD includes a first electrode 16 (¶ 0065; Fig. 3A), a first semiconductor layer 11 (¶ 0065, Fig. 3A), an emission layer 12 (¶ 0065, Fig. 3A), a second semiconductor layer 13 (¶ 0065, Fig. 3A) and a second electrode 15 (¶ 0065, Fig. 3A) disposed on top of each other.
Regarding claim 15, Tae (Fig. 10) discloses the display device according to claim 1, wherein each of the plurality of sub pixels includes a plurality of light emitting diodes LD connected in parallel (Figs. 6A-6E).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Tae as applied to claims 1, 4, and 5 above, and further in view of US 2019/0393291 A1 to Jeon et al. (hereinafter “Jeon”).
Regarding claim 6, Tae (Fig. 10) discloses the display device according to claim 5, wherein the capacitor Cst includes: a second capacitor electrode UE (¶ 0183) disposed on a same layer as a gate electrode GE (¶ 0183) of the transistor T1; and a third capacitor electrode LE (¶ 0183) disposed on a same layer as a source electrode SE (¶ 0184) and a drain electrode DE (¶ 0184) of the transistor (Fig. 10).
Tae fails to expressly disclose: a first capacitor electrode disposed on a same layer as the light shielding layer. In the same field of endeavor, Jeon (Fig. 4) discloses a display device including a first capacitor electrode 155a (¶ 0099) disposed on a same layer as a light shielding layer 120 (¶ 0075), a second capacitor electrode 157 (¶ 0099), and a third capacitor electrode 159 (¶ 0099). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a first capacitor electrode a disclosed by Jeon in the display device of Tae for the purpose of providing noise reduction without increasing circuit footprint (Jeon, ¶ 0099).
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tae as applied to claim 1 above, and further in view of US 2007/0131989 A1 to Liu et al. (hereinafter “Liu”).
Regarding claim 10, Tae (Figs. 10, 6A-6E) discloses the display device according to claim 1, further comprising: a plurality of scan lines Si (Fig. 6D; ¶ 0115) connected to the plurality of sub pixels, wherein the plurality of scan lines includes: a first line part extending in a first direction in the active area and the non-active area (Fig. 6D; ¶¶ 0094, 0101, 0105).
Tae fails to expressly disclose: a first protruding part disposed in the non-active area and extending in a second direction intersecting the first direction from the first line part. In the same field of endeavor, Liu (Fig. 6B) discloses a display device including device lines 250 (¶ 0042) with a first protruding part 254 (¶ 0042) disposed in a non-active area (Fig. 6B) and extending in a second direction (direction from left to right of Fig. 6B) intersecting the first direction (direction from top to bottom of Fig. 6B) from a first line part (part of 250 extending away from end). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first protruding part as disclosed by Liu in the display device scan lines of Tae for the purpose of reducing electrostatic charges (¶ 0042; ¶ 0045 - teachings can be applied to data lines and scan lines).
Regarding claim 11, Tae and Liu disclose the display device according to claim 10, Tae (Figs. 10, 6A-6E) discloses further comprising: a sensing transistor T2 (¶ 0117; Fig. 6D) disposed on the substrate, wherein the plurality of scan lines Si is connected to a gate electrode of the sensing transistor T2 (Fig. 6D).
Regarding claim 12, Tae and Liu disclose the display device according to claim 11, Tae (Fig. 10, 6A-6E) discloses further comprising: a plurality of reference lines Dj (¶ 0115; Fig. 6D) connected to the plurality of sub pixels, wherein the plurality of reference lines includes: a second line part extending in the second direction in the active area and the non-active area (Fig. 6D; ¶¶ 0094, 0101, 0105). Tae and Liu fails to expressly disclose: a second protruding part disposed in the non-active area and extending in the first direction from the second line part. Liu (Fig. 6B) does disclose including device lines 250 (¶ 0042) with a protruding part 254 (¶ 0042) disposed in a non-active area (Fig. 6B) and extending in a first direction (direction from left to right of Fig. 6B) intersecting the second direction (direction from top to bottom of Fig. 6B) from a first line part (part of 250 extending away from end). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a second protruding part as disclosed by Liu in the display device reference lines of Tae for the purpose of reducing electrostatic charges (¶ 0042; ¶ 0045 - teachings can be applied to different types of lines).
Regarding claim 13, Tae and Liu disclose the display device according to claim 12, Tae (Figs. 10, 6D) discloses further wherein the plurality of reference lines Dj (Fig. 6D) is connected to a drain electrode of the sensing transistor T2 (Fig. 6D).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2024/0203315 A1 to Hong et al., US 2017/0338211 A1 to Lin et al., US 2021/0407970 A1 to Lee et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CANDICE Y. CHAN
Examiner
Art Unit 2813
13 March 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights