DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Applicant cancelled claims 1-20; and added claims 21-40 on 12/28/2023.
Claim Objections
At the following locations, indicated by the notation [claim(s), line(s)], please make the following changes to provide better clarity, proper grammar, or proper antecedent basis:
[27, 2] change “the local interconnect” to “a local interconnect”.
[28, 2] change “a local interconnect” to “the local interconnect”.
[32, 1] change “the conductive layer” to “a conductive layer”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 26-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as lacking antecedent basis for the limitations, "the first portion of the trench isolation layer” (Claim 26, Lines 15 and Claim 26, Lines 16-17). It is unclear the term, “the first portion of the trench isolation layer”, is the portion of the “first trench isolation region” (Claim 26, Line 7), “second trench isolation region” (Claim 26, Line 9), or “third trench isolation region” (Claim 26, Line 7). Examiner interprets “the first portion of the trench isolation layer” to mean the first trench isolation region. In addition, claims 26-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as lacking antecedent basis for the limitations, "the second portion of the trench isolation layer” (Claim 26, Lines 19 and Claim 26, Lines 20-21). It is unclear the term, “the second portion of the trench isolation layer”, is the portion of the “first trench isolation region” (Claim 26, Line 7), “second trench isolation region” (Claim 26, Line 9), or “third trench isolation region” (Claim 26, Line 7). Examiner interprets “the second portion of the trench isolation layer” to mean the second trench isolation region. Furthermore, claims 26-35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as lacking antecedent basis for the limitations, "the third portion of the trench isolation layer” (Claim 26, Lines 25 and Claim 26, Lines 26-27). It is unclear the term, “the third portion of the trench isolation layer”, is the portion of the “first trench isolation region” (Claim 26, Line 7), “second trench isolation region” (Claim 26, Line 9), or “third trench isolation region” (Claim 26, Line 7). Examiner interprets “the third portion of the trench isolation layer” to mean the third trench isolation region. Lastly, claims 27-35 depend from claim 26 and inherit its deficiencies.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 26 and 33-35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2019/0103304) (hereafter Lin).
Regarding claim 26, Lin discloses an integrated circuit structure, comprising:
a first semiconductor fin (second 52 from the left corner of Fig. 17A, paragraph 0052) first having a first side (left side of second 52 from the left corner of Fig. 17A) and a second side (right side of second 52 from the left corner of Fig. 17A), the second side (right side of second 52 from the left corner of Fig. 17A) laterally opposite the first side (left side of second 52 from the left corner of Fig. 17A);
a second semiconductor fin (third 52 from the left corner of Fig. 17A, paragraph 0052) laterally spaced apart from the first semiconductor fin (second 52 from the left corner of Fig. 17A), the second semiconductor fin having a first side (left side of third 52 from the left corner of Fig. 17A) and a second side (right side of third 52 from the left corner of Fig. 17A), the second side (right side of third 52 from the left corner of Fig. 17A) laterally opposite the first side (left side of third 52 from the left corner of Fig. 17A);
a first trench isolation region (second 56 from the left corner of Fig. 17A, paragraph 0057) adjacent to a lower portion of the first side (left side of second 52 from the left corner of Fig. 17A) of the first semiconductor fin (second 52 from the left corner of Fig. 17A);
a second trench isolation region (fourth 56 from the left corner of Fig. 17A, paragraph 0057) adjacent to a lower portion of the second side (right side of third 52 from the left corner of Fig. 17A) of the second semiconductor fin (third 52 from the left corner of Fig. 17A);
a third trench isolation region (third 56 from the left corner of Fig. 17A, paragraph 0057) adjacent to a lower portion of the second side (right side of second 52 from the left corner of Fig. 17A) of the first semiconductor fin (second 52 from the left corner of Fig. 17A) and adjacent to a lower portion of the first side (left side of third 52 from the left corner of Fig. 17A) of the second semiconductor fin (third 52 from the left corner of Fig. 17A);
a first isolation structure (second 58 from the left corner of Fig. 17A, paragraph 0024) laterally spaced apart from the first side (left side of second 52 from the left corner of Fig. 17A) of the first semiconductor fin (second 52 from the left corner of Fig. 17A) and in the first portion of the trench isolation layer (second 56 from the left corner of Fig. 17A), the first isolation structure (second 58 from the left corner of Fig. 17A) having a bottom surface below a top surface of the first portion of the trench isolation layer (second 56 from the left corner of Fig. 17A), and the first isolation structure (second 58 from the left corner of Fig. 17A) having a first dielectric plug (second 60 from the left corner of Fig. 17A, paragraph 0057) thereon;
a second isolation structure (fourth 58 from the left corner of Fig. 17A, paragraph 0024) laterally spaced apart from the second side (right side of third 52 from the left corner of Fig. 17A) of the second semiconductor fin (third 52 from the left corner of Fig. 17A) and in the second portion of the trench isolation layer (fourth 56 from the left corner of Fig. 17A), the second isolation structure (fourth 58 from the left corner of Fig. 17A) having a bottom surface below a top surface of the second portion of the trench isolation layer (fourth 56 from the left corner of Fig. 17A), and the second isolation structure (fourth 58 from the left corner of Fig. 17A) having a second dielectric plug (fourth 60 from the left corner of Fig. 17A, paragraph 0057) thereon;
a third isolation structure (third 58 from the left corner of Fig. 17A, paragraph 0024) laterally between the second side (right side of second 52 from the left corner of Fig. 17A) of the first semiconductor fin (second 52 from the left corner of Fig. 17A) and the first side (left side of third 52 from the left corner of Fig. 17A) of the second semiconductor fin (third 52 from the left corner of Fig. 17A), the third isolation structure in the third portion of the trench isolation layer (third 56 from the left corner of Fig. 17A), and the third isolation structure (third 58 from the left corner of Fig. 17A) having a bottom surface below a top surface of the third portion of the trench isolation layer (third 56 from the left corner of Fig. 17A);
and a gate structure (92 and 94 in Fig. 17A, paragraph 0052) over the first semiconductor fin (second 52 from the left corner of Fig. 17A) and over the second semiconductor fin (third 52 from the left corner of Fig. 17A), the gate structure (92 and 94 in Fig. 17A) laterally between the first isolation structure (second 58 from the left corner of Fig. 17A) and the second isolation structure (fourth 58 from the left corner of Fig. 17A).
Regarding claim 33, Lin further discloses the integrated circuit structure of claim 26, wherein the gate structure (92 and 94 in Fig. 17A) comprises a high-k gate dielectric layer 92 (Fig. 17A, paragraph 0052) along less than an entirety of sides of the first isolation structure (second 58 from the left corner of Fig. 17A), the second isolation structure (fourth 58 from the left corner of Fig. 17A), and the third isolation structure (third 58 from the left corner of Fig. 17A).
Regarding claim 34, Lin further discloses the integrated circuit structure of claim 26, wherein the first dielectric plug (second 60 from the left corner of Fig. 17A) and the second dielectric plug (fourth 60 from the left corner of Fig. 17A, paragraph 0025) have a composition different (see paragraph 0025, wherein “the dielectric liner 58 may comprise SiOC with more than 10% by weight of carbon, and the dielectric material 60 may comprise SiOC with less than 10% by weight of carbon”) than a composition of the first isolation structure (second 58 from the left corner of Fig. 17A), the second isolation structure (fourth 58 from the left corner of Fig. 17A), and the third isolation structure (third 58 from the left corner of Fig. 17A).
Regarding claim 35, Lin further discloses the integrated circuit structure of claim 26, wherein the first semiconductor fin (second 52 from the left corner of Fig. 17A) and the second semiconductor fin (third 52 from the left corner of Fig. 17A) comprise silicon (see paragraph 0019, wherein “silicon wafer”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 27 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 26 above, and further in view of Chiang et al. (US 2020/0243665) (hereafter Chiang).
Regarding claim 27, Lin discloses the integrated circuit structure of claim 26, further comprising: a conductive layer on the gate structure and vertically over the third isolation structure; the local interconnect laterally between the first dielectric plug and the second dielectric plug.
Chiang discloses a conductive layer 162 (Fig. 2E, paragraph 0071) on the gate structure 156 (Fig. 2E, paragraph 0071) and vertically over the third isolation structure (third 118 from the left corner of Fig. 2E, paragraph 0074); the local interconnect 162 (Fig. 2E) laterally between the first dielectric plug (left 120 in Fig. 2E, paragraph 0074) and the second dielectric plug (right 120 in Fig. 2E, paragraph 0074).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin to form a conductive layer on the gate structure and vertically over the third isolation structure; the local interconnect laterally between the first dielectric plug and the second dielectric plug, as taught by Chiang, since the conductive layer 162 (Fig. 8E, paragraph 0110) is used to reduce the resistance of the gate electrode layer 156 (Fig. 8E, paragraph 0110).
Regarding claim 28, Lin in view of Chiang discloses the integrated circuit structure of claim 27, however Lin does not disclose the conductive layer is a local interconnect.
Chiang discloses the conductive layer 162 (Fig. 2E, paragraph 0071) is a local interconnect 162 (Fig. 2E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin to form the conductive layer being a local interconnect, as taught by Chiang, since the conductive layer 162 (Fig. 8E, paragraph 0110) is used to reduce the resistance of the gate electrode layer 156 (Fig. 8E, paragraph 0110).
Claims 29-32 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Chiang as applied to claims 26 and 27 above, and further in view of Webb et al. (US 2016/0233298) (hereafter Webb).
Regarding claim 29, Lin in view of Chiang discloses the integrated circuit structure of claim 27, however Lin and Chiang do not disclose a conductive contact on the conductive layer.
Webb discloses a conductive contact 814 (Fig. 8A, paragraph 0056) on the conductive layer 854 (Fig. 8A, paragraph 0056).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Chiang to form a conductive contact on the conductive layer, as taught by Webb, since a conductive contact 814 (Webb, Fig. 8A, paragraph 0056) provides electrical connection between a gate and other devices.
Regarding claim 30, Lin in view of Chiang and Webb discloses the integrated circuit structure of claim 29, however Lin and Chiang do not disclose a conductive interconnect on and coupled to the conductive contact.
Webb discloses a conductive interconnect 860 (Fig. 8A, paragraph 0056) on and coupled to the conductive contact 814 (Fig. 8A, paragraph 0056).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Chiang to form a conductive interconnect on and coupled to the conductive contact, as taught by Webb, since a conductive contact 814 (Webb, Fig. 8A, paragraph 0056) and a conductive interconnect 860 (Webb, Fig. 8A, paragraph 0056) provide electrical connection between a gate and other devices.
Regarding claim 31, Lin in view of Chiang and Webb discloses the integrated circuit structure of claim 30, however Lin and Chiang do not disclose a conductive via between the conductive interconnect and the conductive contact.
Webb discloses a conductive via 816 (Fig. 8A, paragraph 0056) between the conductive interconnect 860 (Fig. 8A, paragraph 0056) and the conductive contact 814 (Fig. 8A, paragraph 0056).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Chiang to form a conductive via between the conductive interconnect and the conductive contact, as taught by Webb, since a conductive contact 814 (Webb, Fig. 8A, paragraph 0056), a conductive via 816 (Webb, Fig. 8A, paragraph 0056), and a conductive interconnect 860 (Webb, Fig. 8A, paragraph 0056) provide electrical connection between a gate and other devices.
Regarding claim 32, Lin in view of Chiang discloses the integrated circuit structure of claim 26, however Lin and Chiang do not disclose the conductive layer is directly on a top of the third isolation structure.
Webb discloses the conductive layer 854 (Fig. 8A, paragraph 0056) is directly on a top of the third isolation structure (third 820 from the left corner of Fig. 8A, paragraph 0056).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Chiang to form the conductive layer being directly on a top of the third isolation structure, as taught by Webb, since the gate structures 808 (Webb, Fig. 8A, paragraph 0057) are shown as disposed over the protruding fin portions 804 (Webb, Fig. 8A, paragraph 0057), as isolated by self-aligned gate edge isolation structures 820 (Webb, Fig. 8A, paragraph 0057).
Claims 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2019/0103304) (hereafter Lin), in view of Chiang et al. (US 2020/0243665) (hereafter Chiang), in further view of Webb et al. (US 2016/0233298) (hereafter Webb).
Regarding claim 21, Lin discloses an integrated circuit structure, comprising:
a first fin structure (second 52 from the left corner of Fig. 17A, paragraph 0052) having a first side (left side of second 52 from the left corner of Fig. 17A) and a second side (right side of second 52 from the left corner of Fig. 17A), the second side (right side of second 52 from the left corner of Fig. 17A) laterally opposite the first side (left side of second 52 from the left corner of Fig. 17A);
a second fin structure (third 52 from the left corner of Fig. 17A, paragraph 0052) laterally spaced apart from the first fin structure (second 52 from the left corner of Fig. 17A), the second fin structure having a first side (left side of third 52 from the left corner of Fig. 17A) and a second side (right side of third 52 from the left corner of Fig. 17A), the second side (right side of third 52 from the left corner of Fig. 17A) laterally opposite the first side (left side of third 52 from the left corner of Fig. 17A);
a trench isolation layer 56 (Fig. 17A, paragraph 0057) having a first portion (second 56 from the left corner of Fig. 17A, paragraph 0057) adjacent to a lower portion of the first side (left side of second 52 from the left corner of Fig. 17A) of the first fin structure (second 52 from the left corner of Fig. 17A), the trench isolation layer 56 (Fig. 17A) having a second portion (fourth 56 from the left corner of Fig. 17A, paragraph 0057) adjacent to a lower portion of the second side of the second fin structure (third 52 from the left corner of Fig. 17A), and the trench isolation layer 56 (Fig. 17A) having a third portion (third 56 from the left corner of Fig. 17A, paragraph 0057) adjacent to a lower portion of the second side (right side of second 52 from the left corner of Fig. 17A) of the first fin structure (second 52 from the left corner of Fig. 17A) and adjacent to a lower portion of the first side (left side of third 52 from the left corner of Fig. 17A) of the second fin structure (third 52 from the left corner of Fig. 17A);
a first gate endcap isolation structure (second 58 from the left corner of Fig. 17A, paragraph 0024) laterally spaced apart from the first side (left side of second 52 from the left corner of Fig. 17A) of the first fin structure (second 52 from the left corner of Fig. 17A) and in the first portion (second 56 from the left corner of Fig. 17A) of the trench isolation layer 56 (Fig. 17A), the first gate endcap isolation structure (second 58 from the left corner of Fig. 17A) having a bottom surface below a top surface of the first portion (second 56 from the left corner of Fig. 17A) of the trench isolation layer, and the first gate endcap isolation structure (second 58 from the left corner of Fig. 17A) having a first dielectric plug (second 60 from the left corner of Fig. 17A, paragraph 0025) thereon;
a second gate endcap isolation structure (fourth 58 from the left corner of Fig. 17A, paragraph 0024) laterally spaced apart from the second side (right side of third 52 from the left corner of Fig. 17A) of the second fin structure (third 52 from the left corner of Fig. 17A) and in the second portion (fourth 56 from the left corner of Fig. 17A) of the trench isolation layer, the second gate endcap isolation structure (fourth 58 from the left corner of Fig. 17A) having a bottom surface below a top surface of the second portion (fourth 56 from the left corner of Fig. 17A) of the trench isolation layer, and the second gate endcap isolation structure (fourth 58 from the left corner of Fig. 17A) having a second dielectric plug thereon (fourth 60 from the left corner of Fig. 17A, paragraph 0025);
a third gate endcap isolation structure (third 58 from the left corner of Fig. 17A, paragraph 0024) laterally between the second side (right side of second 52 from the left corner of Fig. 17A) of the first fin structure (second 52 from the left corner of Fig. 17A) and the first side (left side of third 52 from the left corner of Fig. 17A) of the second fin structure (third 52 from the left corner of Fig. 17A), the third gate endcap isolation structure (third 58 from the left corner of Fig. 17A) in the third portion (third 56 from the left corner of Fig. 17A) of the trench isolation layer, and the third gate endcap isolation structure (third 58 from the left corner of Fig. 17A) having a bottom surface below a top surface of the third portion (third 56 from the left corner of Fig. 17A) of the trench isolation layer; and
a gate structure (92 and 94 in Fig. 17A, paragraph 0052) over the first fin structure (second 52 from the left corner of Fig. 17A) and over the second fin structure (third 52 from the left corner of Fig. 17A), the gate structure 92 and 94 in Fig. 17A) laterally between the first gate endcap isolation structure (second 58 from the left corner of Fig. 17A) and the second gate endcap isolation structure (fourth 58 from the left corner of Fig. 17A).
Lin does not disclose a local interconnect on the gate structure and vertically over the third gate endcap isolation structure, and the local interconnect laterally between the first dielectric plug and the second dielectric plug.
Chiang discloses a local interconnect 162 (Fig. 2E, paragraph 0071) on the gate structure 156 (Fig. 2E, paragraph 0071) and vertically over the third gate endcap isolation structure (third 118 from the left corner of Fig. 2E, paragraph 0074), and the local interconnect 162 (Fig. 2E) laterally between the first dielectric plug (left 120 in Fig. 2E, paragraph 0074) and the second dielectric plug (right 120 in Fig. 2E, paragraph 0074).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin to form a local interconnect on the gate structure and vertically over the third gate endcap isolation structure, and the local interconnect laterally between the first dielectric plug and the second dielectric plug, as taught by Chiang, since the conductive layer 162 (Fig. 8E, paragraph 0110) is used to reduce the resistance of the gate electrode layer 156 (Fig. 8E, paragraph 0110).
Lin and Chiang do not disclose a gate contact on the local interconnect; and
a metal interconnect over and coupled to the gate contact.
Webb discloses a gate contact 814 (Fig. 8A, paragraph 0056) on the local interconnect 854 (Fig. 8A, paragraph 0056);
a metal interconnect 860 (Fig. 8A, paragraph 0056) over and coupled to the gate contact 814 (Fig. 8A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Chiang to form a gate contact on the local interconnect; and a metal interconnect over and coupled to the gate contact, as taught by Webb, since a gate contact 814 (Webb, Fig. 8A, paragraph 0056) and a metal interconnect 860 (Webb, Fig. 8A, paragraph 0056) provide electrical connection between a gate and other devices.
Regarding claim 22, Lin in view of Chiang and Webb discloses the integrated circuit structure of claim 21, however Lin and Chiang do not disclose the local interconnect is directly on a top of the third gate endcap isolation structure.
Webb discloses the local interconnect 854 (Fig. 8A, paragraph 0056) is directly on a top of the third gate endcap isolation structure (third 820 from the left corner of Fig. 8A, paragraph 0056).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Chiang to form the local interconnect is directly on a top of the third gate endcap isolation structure, as taught by Webb, since the gate structures 808 (Webb, Fig. 8A, paragraph 0057) are shown as disposed over the protruding fin portions 804 (Webb, Fig. 8A, paragraph 0057), as isolated by self-aligned gate edge isolation structures 820 (Webb, Fig. 8A, paragraph 0057).
Regarding claim 23, Lin further discloses the integrated circuit structure of claim 21, wherein the gate structure (92 and 94 in Fig. 17A) comprises a high-k gate dielectric layer 92 (Fig. 17A) along less than an entirety of sides of the first gate endcap isolation structure (second 58 from the left corner of Fig. 17A), the second gate endcap isolation structure (fourth 58 from the left corner of Fig. 17A), and the third gate endcap isolation structure (third 58 from the left corner of Fig. 17A).
Regarding claim 24, Lin further discloses the integrated circuit structure of claim 21, wherein the first dielectric plug (second 60 from the left corner of Fig. 17A) and the second dielectric plug (fourth 60 from the left corner of Fig. 17A) have a composition (see paragraph 0025, wherein “the dielectric liner 58 may comprise SiOC with more than 10% by weight of carbon, and the dielectric material 60 may comprise SiOC with less than 10% by weight of carbon”) different than a composition of the first gate endcap isolation structure (second 58 from the left corner of Fig. 17A), the second gate endcap isolation structure (fourth 58 from the left corner of Fig. 17A), and the third gate endcap isolation structure (third 58 from the left corner of Fig. 17A).
Regarding claim 25, Lin in view of Chiang and Webb discloses the integrated circuit structure of claim 21, however Lin and Chiang do not disclose a gate contact via between the metal interconnect and the gate contact.
Webb discloses a gate contact via 816 (Fig. 8A, paragraph 0056) between the metal interconnect 860 (Fig. 8A, paragraph 0056) and the gate contact 814 (Fig. 8A, paragraph 0056).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Chiang to form a gate contact via between the metal interconnect and the gate contact, as taught by Webb, since a gate contact 814 (Webb, Fig. 8A, paragraph 0056), a gate contact via 816 (Webb, Fig. 8A, paragraph 0056), and a metal interconnect 860 (Webb, Fig. 8A, paragraph 0056) provide electrical connection between a gate and other devices.
Claims 36-40 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US 2020/0243665) (hereafter Chiang), in view of Lin et al. (US 2019/0103304) (hereafter Lin), in further view of Webb et al. (US 2016/0233298) (hereafter Webb).
Regarding claim 36, Chiang discloses an integrated circuit structure, comprising:
a first nanowire (third 106 from the left corner of Fig. 8E, paragraph 0021; and see paragraph 0025, wherein “thickness of each of the second semiconductor layers 106 is in a range from about 1.5 nm to about 20 nm”) having a first side (left side of third 106 from the left corner of Fig. 8E) and a second side (right side of third 106 from the left corner of Fig. 8E), the second side laterally opposite the first side;
a second nanowire (fourth 106 from the left corner of Fig. 8E, paragraph 0021) laterally spaced apart from the first nanowire (third 106 from the left corner of Fig. 8E), the second nanowire having a first side (left side of fourth 106 from the left corner of Fig. 8E) and a second side (right side of fourth 106 from the left corner of Fig. 8E), the second side laterally opposite the first side;
a trench isolation layer 114 (Fig. 8E, paragraph 0033) having a first portion (second 114 from the left corner of Fig. 8E) adjacent to the first side (left side of third 106 from the left corner of Fig. 8E) of the first nanowire, the trench isolation layer 114 (Fig. 8E) having a second portion (fourth 114 from the left corner of Fig. 8E) adjacent to the second side (right side of fourth 106 from the left corner of Fig. 8E) of the second nanowire, and the trench isolation layer 114 (Fig. 8E) having a third portion (third 114 from the left corner of Fig. 8E) adjacent to the second side (right side of third 106 from the left corner of Fig. 8E) of the first nanowire and adjacent to the first side (left side of fourth 106 from the left corner of Fig. 8E) of the second nanowire;
a first gate endcap isolation structure (second 118 from the left corner of Fig. 8E, paragraph 0033) laterally spaced apart from the first side (left side of third 106 from the left corner of Fig. 8E) of the first nanowire, and the first gate endcap isolation structure (second 118 from the left corner of Fig. 8E) having a first dielectric plug (left 120 in Fig. 8E, paragraph 0037) thereon;
a second gate endcap isolation structure (fourth 118 from the left corner of Fig. 8E, paragraph 0033) laterally spaced apart from the second side (right side of fourth 106 from the left corner of Fig. 8E) of the second nanowire, and the second gate endcap isolation structure having a second dielectric plug (right 120 in Fig. 8E, paragraph 0037) thereon;
a third gate endcap isolation structure (third 118 from the left corner of Fig. 8E, paragraph 0033) laterally between the second side (right side of third 106 from the left corner of Fig. 8E) of the first nanowire and the first side (left side of fourth 106 from the left corner of Fig. 8E) of the second nanowire;
a gate structure (154 and 156 in Fig. 8E, paragraph 0065) surrounding a channel region (portion of third 106 from the left corner of Fig. 8E vertically below 156 in Fig. 8E) of the first nanowire (third 106 from the left corner of Fig. 8E) and surrounding a channel region (portion of fourth 106 from the left corner of Fig. 8E vertically below 156 in Fig. 8E) of the second nanowire (fourth 106 from the left corner of Fig. 8E), the gate structure (154 and 156 in Fig. 8E) laterally between the first gate endcap isolation structure (second 118 from the left corner of Fig. 8E) and the second gate endcap isolation structure (fourth 118 from the left corner of Fig. 8E); and
a local interconnect 162 (Fig. 8E, paragraph 0071) on the gate structure (154 and 156 in Fig. 8E) and vertically over the third gate endcap isolation structure (third 118 from the left corner of Fig. 8E), and the local interconnect 162 (Fig. 8E) laterally between the first dielectric plug (left 120 in Fig. 8E) and the second dielectric plug (right 120 in Fig. 8E).
Chiang does not disclose a first gate endcap isolation structure in the first portion of the trench isolation layer, the first gate endcap isolation structure having a bottom surface below a top surface of the first portion of the trench isolation layer;
a second gate endcap isolation structure in the second portion of the trench isolation layer, the second gate endcap isolation structure having a bottom surface below a top surface of the second portion of the trench isolation layer; and
the third gate endcap isolation structure in the third portion of the trench isolation layer, and the third gate endcap isolation structure having a bottom surface below a top surface of the third portion of the trench isolation layer.
Lin discloses a first gate endcap isolation structure (second 58 from the left corner of Fig. 17A, paragraph 0024) in the first portion (second 56 from the left corner of Fig. 17A) of the trench isolation layer 56 (Fig. 17A), the first gate endcap isolation structure (second 58 from the left corner of Fig. 17A) having a bottom surface below a top surface of the first portion (second 56 from the left corner of Fig. 17A) of the trench isolation layer;
a second gate endcap isolation structure (fourth 58 from the left corner of Fig. 17A, paragraph 0024) in the second portion (fourth 56 from the left corner of Fig. 17A) of the trench isolation layer 56 (Fig. 17A), the second gate endcap isolation structure (fourth 58 from the left corner of Fig. 17A) having a bottom surface below a top surface of the second portion (fourth 56 from the left corner of Fig. 17A) of the trench isolation layer; and
the third gate endcap isolation structure (third 58 from the left corner of Fig. 17A, paragraph 0024) in the third portion (third 56 from the left corner of Fig. 17A) of the trench isolation layer, and the third gate endcap isolation structure (third 58 from the left corner of Fig. 17A) having a bottom surface below a top surface of the third portion (third 56 from the left corner of Fig. 17A) of the trench isolation layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang to form a first gate endcap isolation structure in the first portion of the trench isolation layer, the first gate endcap isolation structure having a bottom surface below a top surface of the first portion of the trench isolation layer; a second gate endcap isolation structure in the second portion of the trench isolation layer, the second gate endcap isolation structure having a bottom surface below a top surface of the second portion of the trench isolation layer; and the third gate endcap isolation structure in the third portion of the trench isolation layer, and the third gate endcap isolation structure having a bottom surface below a top surface of the third portion of the trench isolation layer, as taught by Lin, since remaining portions of the dielectric liner 56 (Lin, Fig. 27A, paragraph 0062), lower portions of the dielectric liner 58 (Lin, Fig. 27A, paragraph 0062), and lower portions of the dielectric material 60 (referred to collectively as isolation region 64) (Lin, Fig. 27A, paragraph 0062) provide electrical isolation between adjacent fins 52 (Lin, Fig. 27A, paragraph 0062) and may further provide STI regions between the fins 52 (Lin, Fig. 27A, paragraph 0062).
Chiang and Lin does not disclose a gate contact on the local interconnect; and
a metal interconnect over and coupled to the gate contact.
Webb discloses a gate contact 816 (Fig. 8A, paragraph 0056) on the local interconnect 854 (Fig. 8A, paragraph 0056);
a metal interconnect 860 (Fig. 8A, paragraph 0056) over and coupled to the gate contact 814 (Fig. 8A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang in view of Lin to form a gate contact on the local interconnect; and a metal interconnect over and coupled to the gate contact, as taught by Webb, since a gate contact 814 (Webb, Fig. 8A, paragraph 0056) and a metal interconnect 860 (Webb, Fig. 8A, paragraph 0056) provide electrical connection between a gate and other devices.
Regarding claim 37, Chiang in view of Lee and Webb discloses the integrated circuit structure of claim 36, however Chiang and Lee do not disclose the local interconnect is directly on a top of the third gate endcap isolation structure.
Webb discloses the local interconnect 854 (Fig. 8A, paragraph 0056) is directly on a top of the third gate endcap isolation structure (third 820 from the left corner of Fig. 8A, paragraph 0056).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin in view of Chiang to form the local interconnect is directly on a top of the third gate endcap isolation structure, as taught by Webb, since the gate structures 808 (Webb, Fig. 8A, paragraph 0057) are shown as disposed over the protruding fin portions 804 (Webb, Fig. 8A, paragraph 0057), as isolated by self-aligned gate edge isolation structures 820 (Webb, Fig. 8A, paragraph 0057).
Regarding claim 38, Chiang further discloses the integrated circuit structure of claim 36, wherein the gate structure (154 and 156 in Fig. 8E, paragraph 0065) comprises a high-k gate dielectric layer 154 (Fig. 8E, paragraph 0067).
Chiang does not disclose a high-k gate dielectric layer along less than an entirety of sides of the first gate endcap isolation structure , the second gate endcap isolation structure, and the third gate endcap isolation structure.
Lin discloses a high-k gate dielectric layer 92 (Fig. 17A, paragraph 0052) along less than an entirety of sides of the first gate endcap isolation structure (second 58 from the left corner of Fig. 17A), the second gate endcap isolation structure (fourth 58 from the left corner of Fig. 17A), and the third gate endcap isolation structure (third 58 from the left corner of Fig. 17A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang to form a high-k gate dielectric layer along less than an entirety of sides of the first gate endcap isolation structure , the second gate endcap isolation structure, and the third gate endcap isolation structure, as taught by Lin, since the remaining portions of material of the gate electrodes 94 (Lin, Fig. 17A, paragraph 0053) and the gate dielectric layers 92 (Lin, Fig. 17A, paragraph 0053) thus form replacement gates of the resulting FinFETs.
Regarding claim 39, Chiang further discloses the integrated circuit structure of claim 36, wherein the first dielectric plug (left 120 in Fig. 8E) and the second dielectric plug (right 120 in Fig. 8E) have a composition (see paragraph 0039, wherein “hafnium oxide (HfO.sub.2), zirconium oxide (ZrO.sub.2), aluminum oxide (Al.sub.2O.sub.3), hafnium alumina oxide (HfAlOx), hafnium silicon oxide (HfSiOx), hafnium silicon oxynitride, hafnium tantalum oxide (HfTaO.sub.x), hafnium titanium oxide (HfTiOx), hafnium zirconium oxide (HfZrOx), or the like“) different than a composition (see paragraph 0038, wherein “silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbon oxynitride (SiCON), another applicable insulating material, or a combination thereof “) of the first gate endcap isolation structure (second 118 from the left corner of Fig. 8E), the second gate endcap isolation structure (fourth 118 from the left corner of Fig. 8E), and the third gate endcap isolation structure (third 118 from the left corner of Fig. 8E).
Regarding claim 40, Chiang in view of Lin and Webb discloses the integrated circuit structure of claim 36, however Chiang and Lin do not disclose a gate contact via between the metal interconnect and the gate contact.
Webb discloses a gate contact via 816 (Fig. 8A, paragraph 0056) between the metal interconnect 860 (Fig. 8A, paragraph 0056) and the gate contact 814 (Fig. 8A, paragraph 0056).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chiang in view of Lin to form a gate contact via between the metal interconnect and the gate contact, as taught by Webb, since a gate contact 814 (Webb, Fig. 8A, paragraph 0056), a gate contact via 816 (Webb, Fig. 8A, paragraph 0056), and a metal interconnect 860 (Webb, Fig. 8A, paragraph 0056) provide electrical connection between a gate and other devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813