Prosecution Insights
Last updated: October 02, 2026
Application No. 18/516,658

Display Device and Method for Manufacturing the Same

Final Rejection §103
Filed
Nov 21, 2023
Priority
Dec 23, 2022 — RE 10-2022-0183589
Examiner
TRAN, DZUNG
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
891 granted / 1066 resolved
+15.6% vs TC avg
Moderate +6% lift
Without
With
+5.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
57 currently pending
Career history
1134
Total Applications
across all art units

Statute-Specific Performance

§101
5.1%
-34.9% vs TC avg
§103
66.9%
+26.9% vs TC avg
§102
15.0%
-25.0% vs TC avg
§112
9.6%
-30.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1066 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Status of the Claims Applicant’s remarks/amendments of claims 1-8 in the reply filed on June 23rd, 2026, are acknowledged. Claim 1 has been amended. Claims 9-27 have been withdrawn from consideration. Claims 1-27 are pending. Action on merits of claims 1-8 as follows. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 1, 5-7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2020/0243627, hereinafter as Lee ‘627) in view of Yang (US 2021/0167146, hereinafter as Yang ‘146). Regarding Claim 1, Lee ‘627 teaches a display device comprising: a plurality of sub-pixels (pixel array; see Fig. 1; [0043]); a power line configured to supply a voltage (not shown; see para. [0045]); and a plurality of power connection lines (Fig. 3, (AE); [0059]) electrically connecting the plurality of sub-pixels to the power line (see para. [0059]), wherein each of the plurality of sub-pixels includes an anode electrode layer (ANO; [0060]) on a same layer as a corresponding power connection line from the plurality of power connection lines (see Fig. 3), an organic light-emissive layer (OL; [0064]) on the anode electrode layer (ANO), a cathode electrode layer (CAT; [0066]) on the organic light-emissive layer, a passivation layer (PAS2; [0062]) on the cathode electrode layer (CAT), and a structure (BR1; [0062]) on the corresponding power connection line (AE) such that an undercut (Fig. 3, (UC_Annotated)) is formed between the structure and the corresponding power connection line, the cathode electrode layer (CAT) connected to a portion of the corresponding power connection line (AE) corresponding to the undercut. Lee ‘627 is shown to teach all the features of the claim with the exception of explicitly the limitations: “between two adjacent sub-pixels among the plurality of sub-pixels, the organic light-emissive layer, the cathode electrode layer, and the passivation layer of each sub-pixel are respectively disconnected from the organic light-emissive layer, the cathode electrode layer, and the passivation layer of the adjacent sub-pixel”. Yang ‘146 teaches between two adjacent sub-pixels among the plurality of sub-pixels (P1 P2 and P3), the organic light-emissive layer (Fig. 8E, (301); [0054]), the cathode electrode layer (Fig. 8E, (401); [0056]), and the passivation layer (Fig. 8E, (501); [0059]) of each sub-pixel are respectively disconnected from the organic light-emissive layer (302), the cathode electrode layer (402), and the passivation layer (502) of the adjacent sub-pixel (see Fig. 8E). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Lee ‘627 by having between two adjacent sub-pixels among the plurality of sub-pixels, the organic light-emissive layer, the cathode electrode layer, and the passivation layer of each sub-pixel are respectively disconnected from the organic light-emissive layer, the cathode electrode layer, and the passivation layer of the adjacent sub-pixel in order to reduce defects, and/or for simplify a process of an organic light-emitting display apparatus (see para. [0006]) as suggested by Yang ‘146. [AltContent: textbox (UC)][AltContent: arrow] PNG media_image1.png 336 485 media_image1.png Greyscale Fig. 3 (Lee ‘627_Annotated) Regarding Claim 5, Lee ‘627 teaches an outermost boundary of the organic light-emissive layer (OL), an outermost boundary of the cathode electrode layer (CAT), and an outermost boundary of the passivation layer (PAS2), wherein the outermost boundary of the organic light-emissive layer (OL) is inset from the outermost boundary of the passivation layer (PAS2), and the outermost boundary of the cathode electrode layer (CAT) is between the outermost boundary of the organic light-emissive layer (OL) and the outermost boundary of the passivation layer (PAS2) (see Fig. 3). Regarding Claim 6, Lee ‘627 teaches each of the plurality of sub-pixels (OLE) is inset from the outermost boundary of the organic light-emissive layer (OL), the outermost boundary of the cathode electrode layer (CAT), and the outermost boundary of the passivation layer (PAS2). Regarding Claim 7, Lee ‘627 teaches a light-emitting area (see Fig. 3), and the structure (BR1) included in the sub-pixel is in the light-emitting area but non-overlapping with the anode electrode layer (ANO) of the sub-pixel. Regarding Claim 8, Lee ‘627 teaches the power line is a low-potential voltage line (see para. [0045]) and the voltage is a low-potential voltage that is applied to the cathode electrode (CAT) layer included in each of the plurality of sub-pixels via the plurality of power connection lines (AE) (see para. [0059]). Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘627 and Yang ‘146 as applied to claim 1 above, and further in view of Seo (US 2021/0296367, hereinafter as Seo ‘367). Regarding Claim 2, Lee ‘627 and Yang ‘146 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a plurality of data lines, each data line from the plurality of data lines disposed between a pair of adjacent sub-pixels from the plurality of sub-pixels and is non-overlapping with the cathode electrode layer of each of the pair of adjacent sub-pixels”. Seo ‘367 teaches a plurality of data lines (Fig. 2, (DL); [0070]), each data line from the plurality of data lines disposed between a pair of adjacent sub-pixels (SP; [0069]) from the plurality of sub-pixels and is non- overlapping with the cathode electrode layer of each of the pair of adjacent sub-pixels (see Fig. 2). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Lee ‘627 and Yang ‘146 by having a plurality of data lines, each data line from the plurality of data lines disposed between a pair of adjacent sub-pixels from the plurality of sub-pixels and is non- overlapping with the cathode electrode layer of each of the pair of adjacent sub-pixels for the purpose of providing a method of manufacturing a display device that have improved device characteristics (see para. [0009]) as suggested by Seo ‘367. Regarding Claim 3, Lee ‘627 teaches the plurality of data lines (D1 to Dm; [0040]) and the plurality of power connection lines (AE; [0059]) Lee ‘627, Yang ‘146 and Seo ‘367 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the plurality of data lines and the plurality of power connection lines are alternately arranged and are non-overlapping with each other, and extend in a first direction”. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of data lines and the plurality of power connection lines that can be arranged in any order, the plurality of data lines and the plurality of power connection lines are alternately arranged and are non-overlapping with each other, and extend in a first direction involves only routine skill in the art. In re Einstein, 8 USPQ 167. A person of ordinary skills in the art is motivated to perform the arrangement when this allows a good flow with the other steps in the fabrication process. Regarding Claim 4, Seo ‘367 teaches the plurality of sub-pixels (SP; [0069]) are arranged in a matrix form along a first direction and a second direction intersecting the first direction (see Fig. 2), wherein each of the plurality of power connection lines (VDDL; [0070]) extends in the first direction and electrically connect the plurality of sub-pixels (SP) arranged in the first direction to the power line (see Fig. 2). Examiner’s Note Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182. Examiner has cited particular paragraph in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Response to Arguments Applicant’s arguments with respect to claims 1-8, filed on June 23rd, 2026, have been considered but are moot in view of the new ground of rejection. Interviews After Final Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13 Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DZUNG TRAN/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Nov 21, 2023
Application Filed
Apr 06, 2026
Non-Final Rejection mailed — §103
Jun 23, 2026
Response Filed
Sep 01, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
2y 9m to grant Granted Sep 29, 2026
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DISPLAY SUBSTRATE AND METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE
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2y 9m to grant Granted Sep 22, 2026
Patent 12740245
LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
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3y 3m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
89%
With Interview (+5.7%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1066 resolved cases by this examiner. Grant probability derived from career allowance rate.

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