Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato et al. (US Pub. No. 2019/0267370 A1), hereafter referred to as Sato.
As to claim 1, Sato discloses a semiconductor transistor (figs 1-4) comprising a transistor portion (70) and a diode portion (80/120),
wherein the transistor portion (70) includes:
a plurality of trench portions (30) provided in a semiconductor substrate (substrate 10 [0053]);
a drift region (18) of a first conductivity type (n-type) provided in the semiconductor substrate (10);
a base region (region 14) of a second conductivity type (p-type) provided above the drift region (18);
an emitter region (12) of the first conductivity type (n-type) provided on a front surface of the semiconductor substrate (top surface) and having a doping concentration higher than that of the drift region ([0064]); and
a contact region (15) of the second conductivity type (p-type) provided on the front surface of the semiconductor substrate (top surface) above the base region (14; [0063]) and having a doping concentration higher than that of the base region ([0063]),
the diode portion (80/120) includes:
the plurality of trench portions (30);
the drift region (18) of the first conductivity type (n-type);
an anode region (126) of the second conductivity type (p-type) provided above the drift region (18) and having a doping concentration lower than that of the base region ([0092]); and
a second conductivity type region (122) provided on the front surface of the semiconductor substrate (top surface) above the anode region (portion of 122 is above lower corner portion of 126) and having a doping concentration higher than that of the anode region ([0069]),
the diode portion (80/120) includes:
a Schottky junction region (metal/semiconductor Schottky barrier junction formed between 52 and 126) in which the anode region (126) is provided on the front surface of the semiconductor substrate (top surface of 10); and
an Ohmic junction region (128; [0085]) in which the anode region (126) and the second conductivity type region (122) are provided on the front surface of the semiconductor substrate (top surface of 10).
As to claim 2, Sato discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the doping concentration of the anode region is equal to or greater than 2.5E14 cm-3 and equal to or smaller than 1E16 cm-3 ([0100])
As to claim 3, Sato discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the Schottky junction region is provided, in a top view of the semiconductor substrate, in the diode portion at an end of the transistor portion side Schottky junction between 52 and 122/126 at the end portion of region 70).
As to claim 4, Sato discloses the semiconductor device according to claim 1 (paragraphs above),
wherein a width of the Schottky junction region is equal to or smaller than 70 μm in a trench arrangement direction (fig 4, the Schottky junction region is considered to be only the portion of the metal/semiconductor contact between 52/122 that is in the direction of the trench and that is less than 70 μm).
As to claim 5, Sato discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the Schottky junction region is not provided with the second conductivity type region (fig 4, Schottky junction region is only considered to be the region in contact with 126 not second conductivity type region 122).
As to claim 6, Sato discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the second conductivity type region (122) is discretely provided in a trench extending direction (fig 2, singular region 122 is discrete in trench 30 extending direction; additionally, fig 17 and [0144] teach that each diode 120 between adjacent transistor regions 70).
As to claim 7, Sato discloses the semiconductor device according to claim 6 (paragraphs above),
wherein the second conductivity type region (122) is provided to be spaced apart from a side wall of the trench portion (30) in a mesa portion of the semiconductor substrate (10).
As to claim 20, Sato discloses the semiconductor device according to claim 1 (paragraphs above),
wherein the semiconductor substrate is not provided with a lifetime control region including a lifetime killer in the front surface side compared to a center in a depth direction of the semiconductor substrate (fig 4 no lifetime killers are in the front surface side compared to a center).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 13-14 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Mitsuzuka et al. (US Pub. No. 2022/0271152 A1), hereafter referred to as Mitsuzuka.
As to claim 13, Sato discloses the semiconductor device according to claim 1 (paragraphs above),
Sato does not disclose wherein the transistor portion includes a boundary region not provided with the emitter region at an end of the diode portion side in a top view of the semiconductor substrate.
Nonetheless, Mitsuzuka discloses wherein a transistor portion includes a boundary region not provided with the emitter region at an end of the diode portion side in a top view of the semiconductor substrate (figs 3A-B, boundary region 66 without emitter region at end of diode portion 80).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the boundary region of Sato with the region as taught by Mitsuzuka since this will improve the reverse recovery tolerance of the semiconductor device without deteriorating the characteristics of the diode portion.
As to claim 14, Sato in view of Mitsuzuka disclose the semiconductor device according to claim 13 (paragraphs above),
Mitsuzuka further discloses wherein a width of the boundary region in a trench arrangement direction is smaller than a width of the Schottky junction region in the trench arrangement direction (fig 3A-B, width of 13).
As to claim 16, Sato in view of Mitsuzuka disclose the semiconductor device according to claim 13 (paragraphs above),
Sato further discloses wherein, in a top view of the semiconductor substrate, the contact regions (15) and the base regions (14) are alternately provided in the boundary region in a trench extending direction (extending direction of trench 30).
As to claim 17, Sato in view of Mitsuzuka disclose the semiconductor device according to claim 13 (paragraphs above),
Sato does not disclose an accumulation region.
Nonetheless, Mitsuzuka further discloses wherein the transistor portion includes an accumulation region (fig 3B, 16) of the first conductivity type provided below the base region and having a doping concentration higher than that of the drift region ([0095]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the accumulation region of Mitsuzuka in the transistor region of Sato since this will enhance carrier injection promoting effect and reduce the on-voltage of the transistor portion.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato in view of Mitsuzuka et al. (US Pub. No. 2022/0328669 A1), hereafter referred to as Mitsuzuka2.
As to claim 19, Sato discloses the semiconductor device according to claim 1 (paragraphs above),
Sato does not disclose comprising a trench contact portion provided on the front surface of the semiconductor substrate, wherein the second conductivity type region is discretely provided at a lower end of the trench contact portion.
Nonetheless, Mitsuzuka2 discloses a trench contact portion provided on the front surface of the semiconductor substrate, wherein the second conductivity type region is discretely provided at a lower end of the trench contact portion (fig 8B, trench contact 60 at region 14).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a trench contact in the device of Sato as taught by Mitsuzuka2 since this will improve electrical contact between the metal electrode and the second conductivity type region.
Allowable Subject Matter
Claims 8-12, 15, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest wherein the doping concentration of the second conductivity type region is higher than the doping concentration of the contact region, as recited in claim 8 and including the limitations of intervening claim 6 and independent claim 1; or wherein the diode portion includes a reach-through prevention region of the second conductivity type provided above the drift region and having a doping concentration higher than the doping concentration of the anode region and lower than the doping concentration of the second conductivity type region, as recited in claim 9; or wherein the width of the boundary region in the trench arrangement direction is equal to or greater than 1.7 μm and equal to or smaller than 2.3 μm, as recited in claim 15; or wherein the accumulation region is not provided in the boundary region, as recited in claim 18. Claims 10-12 are include allowable subject matter because of their dependence from claim 9.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2018/0108737A1; US Pub. No. 2020/0185520 A1; and US Pub. No. 2016/0005844A1
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 1/21/2026