Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Restriction/Election
Applicant's election without traverse of invention I, claims 1-12 in the reply filed on May 7, 2026 is acknowledged. Claims 13-21 directed to a nonelected invention are withdrawn.
Claim Objections
Claims 1 and 8 are objected to because of the following informalities: claims 1 and 8 both include the limitation: ‘wherein the second conductivity type is different from the second conductivity type”. This statement is a contradiction, and as such, is probably a typographical error. For the purpose of examination, this limitation will be corrected to read: “wherein the second conductivity type is different from the first conductivity type.” Appropriate correction is required.
Claims 1 and 2 are objected to because of the following informalities: lack of antecedent basis for “the direction” [claim1] and for “the first direction” [claim 2] and “the second direction” [claim 2].
Claims 1-12 are objected to because of the following informalities: number and letter labels throughout each of the claims in parentheses. The parentheses and the labels should be removed. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5, 7-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. 20230369432 in view of Cotorogea et al. US 20150349116.
Regarding claim 1, Yang discloses a semiconductor device, comprising:
a substrate having a first conductivity type (figure 2, layer 222 has conductivity type N [0041].)
an epitaxial layer having the first conductivity type located on the substrate (figure 2, epitaxial layer 220, has conductivity type N [0041] and is located on substrate 222);
a first trench and a second trench located in the epitaxial layer (figure 2, elements 218a and 218b are trenches [0042] in the epitaxial layer 220);
a first gate structure including a first gate at least partially located in the first trench, and a first gate dielectric layer between the first gate and the epitaxial layer (the first trench comprises gate 212a which is located in the first trench 211a, and dielectric layer 214a is between the first gate 212a and the epitaxial layer 220);
a second gate structure including a second gate at least partially located in the second trench, and a second gate dielectric layer between the second gate and the epitaxial layer (the second trench comprises gate 212b which is located in the second trench 211b, and dielectric layer 214b is between the second gate 212b and the epitaxial layer 220);
a first body region with a second conductivity type located in the epitaxial layer between the first gate structure and the second gate structure, the first body region being spaced apart from the first gate dielectric layer and being contiguous with the second gate dielectric layer, (figure 2, element 206 is a first body region with a second conductivity type P+ [0041], spaced apart from the first gate dielectric layer 214a and contiguous with the second gate dielectric layer 214b)
wherein the second conductivity type is different from the second conductivity type (See the objection to claim 1 above. If this claim limitation is corrected to read, “wherein the second conductivity type is different from the first conductivity type”, then figure 2 discloses that the first conductivity type is N and the second conductivity type is P);
a first electrode region having the first conductivity type located in the first body region (figure 2 region 204 has N conductivity and is located within the first body region 206);
a third gate structure located on a top surface of the epitaxial layer, wherein the third gate structure partially overlaps the first body region (figure 2, element 208 is a gate structure located on a top surface of the epitaxial layer 220, partially overlapping the first body region 206).
Yang lacks:
wherein in the direction from the epitaxial layer to the substrate, a depth of the first trench in the epitaxial layer is greater than a depth of the second trench in the epitaxial layer
and a second electrode located under the substrate
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However, Cotorogea discloses an analogous type of semiconductor device:
wherein in the direction from the epitaxial layer to the substrate, a depth of the first trench in the epitaxial layer is greater than a depth of the second trench in the epitaxial layer (annotated figure 1B, in the direction from the epitaxial layer 100 to the substrate as indicated by the solid arrow, the depth of the first trench in the epitaxial layer D1 is greater than the depth of the second trench in the epitaxial layer D2, as indicated in annotated figure 1B),
and a second electrode located under the substrate (annotated figure 1B, layer 180 is a back side electrode [0029]).
It would have been obvious to a person of ordinary skill in the art at the time of filing to have a back side electrode and gate trenches with different depths in order to alter the electric field in the epitaxial layer to steer an avalanche current in a direction different from the normal current pathway, protecting the device from damage.
Regarding claim 2, Yang, as modified by Cotorogea, discloses the semiconductor device according to claim 1, wherein an extending direction of the first trench and the second trench is the first direction, and a size of the first trench in the second direction is larger than a size of the second trench in the second direction, wherein the second direction is substantially perpendicular to the first direction (annotated figure 1B below shows the first direction, which is an extending direction of both trenches, and the width of the first trench is greater than the width of the second
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trench in the second direction).
Regarding claim 3, Yang, as modified by Cotorogea, discloses the semiconductor device according to claim 1, wherein the third gate structure partially overlaps the first gate dielectric layer and the third gate structure does not overlap the first gate (Yang figure 2 shows that the lateral gate structure 208 partially overlaps the first gate dielectric layer 214a and does not overlap the first gate 212a).
Regarding claim 5, Yang, as modified by Cotorogea, discloses the semiconductor device according to claim 1, wherein the first gate dielectric layer comprises a first portion on a first sidewall of the first trench, a second portion on a second sidewall of the first trench and a third portion at a bottom of the first trench, wherein the third portion connects the first portion with the second portion (The active cell of Yang figure 2 can comprise a closed cell pattern [0071], as illustrated in Yang figure 4A. An annotated figure showing a cross-section across the entire cell 400 has callouts indicating the positions of the first, second, and third portions, where the third portion connects the first and second portions);
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wherein the semiconductor device further comprises:
a second body region, wherein the first body region and the second body region are respectively located on opposite sides of the first gate structure (the second body region is indicated on annotated figure 2 below where the first body region is to the left of the first portion of the first gate dielectric layer and the second body region is on the right of the second portion of the first gate dielectric);
a fourth gate structure located on the top surface of the epitaxial layer (a fourth gate structure, located on the top surface of the epitaxial layer 220, is indicated by a callout in the annotated figure 2 below);
wherein the third gate structure partially overlaps the first portion and partially overlaps the first body region (see annotated figure 2 below, where the third gate structure 208 overlaps the first portion and partially overlaps the first body region 206);
wherein the fourth gate structure partially overlaps the second portion and partially overlaps the second body region (see annotated figure 2, where the fourth gate structure, indicated by the callout, overlaps the second portion and partially overlaps the second body region, also indicated by callouts).
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Regarding claim 7, Yang, as modified by Cotorogea, discloses the semiconductor device according to claim 1, further comprising: a first spacer and a second spacer located on opposite sides of the third gate structure ,wherein the first spacer is located on a surface of the first gate dielectric layer, the second spacer is located on a surface of the first body region (annotated figure 2 indicates a first spacer and a second spacer, located at opposite sides of the third gate structure, wherein the first spacer is located on a surface of the first gate dielectric 214a and the second spacer is located on the surface of the first body region 206).
Regarding claim 8, Yang discloses a semiconductor device, comprising:
a substrate having a first conductivity type (figure 2, layer 222 has conductivity type N [0041]);
an epitaxial layer having the first conductivity type located on the substrate (figure 2, epitaxial layer 220, has conductivity type N [0041] and is located on substrate 222);
a first trench and a second trench located in the epitaxial layer (figure 2, elements 218a and 218b are trenches [0042] located in the epitaxial layer 220);
a first gate structure including a first gate at least partially located in the first trench, and a first gate dielectric layer between the first gate and the epitaxial layer (the first trench comprises gate 212a which is located in the first trench 211a, and dielectric layer 214a is between the first gate 212a and the epitaxial layer 220);
a second gate structure including a second gate at least partially located in the second trench, and a second gate dielectric layer located between the second gate and the epitaxial layer (the second trench comprises gate 212b which is located in the second trench 211b, and dielectric layer 214b is between the second gate 212b and the epitaxial layer 220);
a first body region with the second conductivity type located in the epitaxial layer between the first gate structure and the second gate structure, the first body region being spaced apart from the first gate dielectric layer and being contiguous with the second gate dielectric layer (figure 2, element 206 is a first body region with a second conductivity type P+ [0041] located in the epitaxial layer 220 between the first and second gate structures 212a and 212b, spaced apart from the first gate dielectric layer 214a and contiguous with the second gate dielectric layer 214b),
and the second conductivity type is different from the second conductivity type (See the objection to claim 1 above. If this claim limitation is corrected to read, “wherein the second conductivity type is different from the first conductivity type”, then figure 2 discloses that the first conductivity type is N and the second conductivity type is P);
a first electrode region having the first conductivity type located in the first body region (figure 2 region 204 has N+ conductivity and is located within the first body region 206);
a third gate structure located on a top surface of the epitaxial layer, wherein the third gate structure partially overlaps the first body region (figure 2, element 208 is a gate structure located on a top surface of the epitaxial layer 220, partially overlapping the first body region 206);
Yang lacks:
wherein a depth of the first gate in the epitaxial layer is greater than a depth of the second gate in the epitaxial layer;
and a second electrode located under the substrate.
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However, Cotorogea discloses an analogous type of semiconductor device:
wherein a depth of the first trench in the epitaxial layer is greater than a depth of the second trench in the epitaxial layer (annotated figure 1B, the depth D1 of the first trench in the epitaxial layer 100 is greater than the depth D2 of the second trench in the epitaxial layer 100, as indicated in annotated figure 1B),
and a second electrode located under the substrate (annotated figure 1B, layer 180 is a back side electrode [0029] located under the substrate).
It would have been obvious to a person of ordinary skill in the art at the time of filing to have a back side electrode and gate trenches with different depths in order to alter the electric field in the epitaxial layer to steer an avalanche current in a direction different from the normal current pathway, protecting the device from damage.
Regarding claim 9, Yang, as modified by Cotorogea, discloses the semiconductor device according to claim 8, wherein an extending direction of the first gate and the second gate is the first direction, and a size of the first gate in the second direction is larger than a size of the second gate in the second direction, wherein the second direction is substantially perpendicular to the first direction (annotated figure 1B, from the rejection of claim 2 above, shows the first direction, which is an extending direction of both trenches and shows that the width of the first trench is greater than the width of the second trench in the second direction which is substantially perpendicular to the first direction).
Regarding claim 10, Yang, as modified by Cotorogea, discloses the semiconductor device according to claim 8, wherein the third gate structure partially overlaps the first gate dielectric layer, and the third gate structure does not overlap the first gate (Yang figure 2 shows that the third gate structure 208 partially overlaps the first gate dielectric layer 214a and does not overlap the first gate 212a).
Regarding claim 12, Yang, as modified by Cotorogea, discloses the semiconductor device according to claim 8, wherein
the first gate dielectric layer comprises a first portion on a first sidewall of the first trench, a second portion on a second sidewall of the first trench and a third portion at a bottom of the first trench , wherein the third portion connects the first portion with the second portion (annotated figure 2 from the rejection of claim 5 above shows that the first gate dielectric layer 214a comprises first second and third portions, as described above, indicated with callouts);
wherein the semiconductor device further comprises:
a second body region, wherein the first body region and the second body region are respectively located on opposite sides of the first gate structure (annotated figure 2 from the rejection of claim 5 above indicates the second body region, where the first body region is to the left of the first portion of the first gate dielectric layer 214a and the second body region on the right of the second portion of the first gate dielectric);
and a fourth gate structure located on the top surface of the epitaxial layer (a fourth gate structure, located on the top surface of the epitaxial layer 220, is indicated by a callout in the annotated figure 2 from the rejection of claim 5);
wherein the third gate structure partially overlaps the first portion and partially overlaps the first body region (annotated figure 2 from the rejection of claim 5 shows that the third gate structure 208 overlaps the first portion, indicated by a callout, and partially overlaps the first body region 206);
wherein the fourth gate structure partially overlaps the second portion and partially overlaps the second body region (annotated figure 2 shows the fourth gate structure, indicated by the callout, overlaps the second portion and partially overlaps the second body region, also indicated by callouts).
Claims 4, 6, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Yang, as modified by Cotorogea, as applied to claims 1, 5, and 8 above, and further in view of Aichinger US 20160260829.
Regarding claim 4, Yang, as modified by Cotorogea, discloses the semiconductor device according to claim 1.
Yang as modified by Cotorogea, lacks a first doped region with the second conductivity type located in the epitaxial layer and contiguous with the first gate dielectric layer, wherein the first doped region is separated from the first body region by the epitaxial layer.
However, Aichinger discloses a similar semiconductor device with a first doped region (figure 6H, 116) with a second conductivity type (p-type) located in the epitaxial layer (figure 6H, 121/122) and contiguous with the first gate dielectric structure (figure 6H, 151a), wherein the first doped region (figure 6H, 116) is separated from the first body region (figure 6H, 115) by the epitaxial region (figure 6H, 121/122).
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to add the doped region of Aichinger to the semiconductor device of Yang, as modified by Cotorogea in order to help steer currents within the device along preferred paths to improve the functioning of the device.
Regarding claim 6, Yang as modified by Cotorogea discloses the semiconductor device according to claim 5,
Yang as modified by Cotorogea lacks:
the semiconductor device further comprises a first doped region and a second doped region, wherein the first doped region and the second doped region are located on opposite sides of the first gate structure respectively portion, wherein
the first doped region and the first body region are separated by the epitaxial layer and is contiguous with the first portion; and wherein
the second doped region and the second body region are separated by the epitaxial layer and the second doped region is contiguous with the second portion.
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However, Aichinger discloses a similar semiconductor device wherein:
the semiconductor device further comprises a first doped region and a second doped region, wherein the first doped region and the second doped region are located on opposite sides of the first gate structure respectively portion (see annotated figure 6H, where these regions are located on opposite sides, right and left, of the first gate structure of trench 350a) wherein
the first doped region (shown in annotated figure 6H) and the first body region (figure 6H, 115) are separated by the epitaxial layer (figure 6H, 121/122) and is contiguous with the first portion(shown in annotated figure 6H – the first portion is the part of 151a enclosed in the circle to the left); and wherein
the second doped region (shown in annotated figure 6H) and the second body region (figure 6H, 115) are separated by the epitaxial layer (figure 6H, 121/122) and the second doped region is contiguous with the second portion (shown in annotated figure 6H – the second portion is the part of 151a enclosed in the circle to the right).
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to add the doped regions of Aichinger to the semiconductor device of Yang, as modified by Cotorogea in order to help steer currents within the device along preferred paths to improve the functioning of the device.
Regarding claim 11, Yang as modified by Cotorogea discloses the semiconductor device according to claim 8,
Yang as modified by Cotorogea lacks a first doped region with the second conductivity type located in the epitaxial layer and contiguous with the first gate dielectric layer, wherein the first doped region (180A) is separated from the first body region by the epitaxial layer.
However, Aichinger discloses a similar semiconductor device with a first doped region (figure 6H, 116) with the second conductivity type (p-type) located in the epitaxial layer (figure 6H, 121/122) and contiguous with the first gate dielectric structure (figure 6H, 151a), wherein the first doped region (figure 6H, 116) is separated from the first body region (figure 6H, 115) by the epitaxial region (figure 6H, 121/122).
Therefore, it would have been obvious to a person having ordinary skill in the art before the time of filing to add the doped region of Aichinger to the semiconductor device of Yang, as modified by Cotorogea in order to help steer currents within the device along preferred paths to improve the functioning of the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Toyoda et al. US 20180076201 (discloses lateral MOSFET and a vertical semiconductor device that are formed on the same semiconductor substrate, invention is directed toward solving breakdown problem), Zundel et al. US 20170110572 (discloses a power semiconductor device with improved robustness toward avalanche conditions), Bobde et al. US 9318587 (disclosure relates to the semiconductor power devices configured to improve the collector-emitter saturation voltage and avoid backside implant), Nakano US 12080760 (discloses SiC power semiconductor with trench gates).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATRINA M H WALJESKI-MOSES whose telephone number is (571)272-0731. The examiner can normally be reached Mon- Fri 7:30 am- 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATRINA WALJESKI-MOSES/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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