DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: plasma is spelled incorrectly as “plasm” in paragraph 46 of the specification, and bonded is spelled incorrectly as “boned” in paragraph 47 of the specification. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation, “wherein when the first surface of the handle wafer is coated with the water, the handle wafer rotates at a first rotational speed; when the second surface of the device wafer is coated with the water, the device wafer rotates at a second rotational speed; and when the first surface of the handle wafer and the second surface of the device wafer are coated with the water, the handle wafer rotates at a third rotational speed, and the device wafer rotates at a fourth rotational speed,” in lines 5-11 of the claim. The meets and bounds of claim 1 are indefinite as the meaning of the word “when” is unclear in the context of this limitation. It is unclear whether “when” has a meaning of ‘in the instance where’ and is used to re-establish and further limit the limitation of lines 3-4 of claim 1, has a meaning of ‘as’ and is used to establish that the rotation occurs during the process of coating the water, or has a meaning of ‘after’ and is used to establish that the rotation occurs after the process of coating the water. In light of the specification, and for the purpose of this office action, the limitation of lines 5-11 of claim 1 is interpreted to have the following meaning: wherein during the process of coating the water, when only the first surface of the handle wafer is coated with the water, the handle wafer rotates at a first rotational speed; when only the second surface of the device wafer is coated with the water, the device wafer rotates at a second rotational speed; and when both the first surface of the handle wafer and the second surface of the device wafer are coated with the water, the handle wafer rotates at a third rotational speed, and the device wafer rotates at a fourth rotational speed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-7, 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (US PGPub 20070184631 A1; hereinafter referred to as “Nakamura”) in view of Shimomura et al. (US PGPub 20100029058 A1; hereinafter referred to as “Shimomura”) and further in view of Hashizume (JP 2008108829 A; hereinafter referred to as “Hashizume”).
Re claim 1: Nakamura teaches a method of wafer bonding, comprising: receiving a handle wafer and a device wafer (para. 28| a bond wafer (device wafer) and a base wafer (handle wafer) are subjected to a bonding process to provide a bonded wafer), and bonding the first surface of the handle wafer and the second surface of the device wafer (FIG. 1d; para. 10). Nakamura fails to teach coating a first surface of the handle wafer, a second surface of the device wafer, or a combination thereof with water, wherein during the process of coating the water, when only the first surface of the handle wafer is coated with the water, the handle wafer rotates at a first rotational speed; when only the second surface of the device wafer is coated with the water, the device wafer rotates at a second rotational speed; and when both the first surface of the handle wafer and the second surface of the device wafer are coated with the water, the handle wafer rotates at a third rotational speed, and the device wafer rotates at a fourth rotational speed.
In a similar field of endeavor, Shimomura teaches a method of bonding substrates comprising: receiving a handle substrate and a device substrate (FIG. 2A1, 2B1: el. 100, 120; para. 113, 114, 142| device substrate 100 and handle substrate 120 are received to be prepared for bonding); coating a first surface of the handle wafer, a second surface of the device wafer, or a combination thereof with water (para. 143|two fluid cleaning, using pure water and nitrogen gas, is performed on at least one bonding surface to coat and clean the bonding surface after plasma activation of the bonding surface). Shimomura further teaches a benefit of coating the bonding surface with water using a two-fluid clean is to improve strength of the bond by removing dust such as organic material on the bonding surface (para. 143).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Nakamura and Shimomura to enable using the water coating and cleaning step of Shimomura in the wafer bonding method of Nakamura for the benefit of improving bond strength by removing dust such as organic material on the bonding surface.
The combination of Nakamura and Shimomura is silent as to wafer rotation during the water coating step and thus fails to disclose wherein during the process of coating the water, when only the first surface of the handle wafer is coated with the water, the handle wafer rotates at a first rotational speed; when only the second surface of the device wafer is coated with the water, the device wafer rotates at a second rotational speed; and when both the first surface of the handle wafer and the second surface of the device wafer are coated with the water, the handle wafer rotates at a third rotational speed, and the device wafer rotates at a fourth rotational speed.
In a similar field of endeavor, Hashizume teaches a method of two fluid cleaning with pure deionized water to remove foreign material from a wafer surface (para. 33: last sentence). Hashizume teaches coating a surface of a device wafer with water, wherein during the process of coating the water, when only the surface of the device wafer is coated with the water, the wafer rotates at a rotational speed (para. 35-38; para. 5|the wafer rotating and coating process of Hashizume is applied to a generic unpatterned or patterned wafer and applies to either a device wafer or a handle wafer). Hashizume further teaches a benefit of rotating a wafer while coating with water is to use centrifugal force to distribute water across the entire wafer surface (para. 36).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings Hashizume with the teachings of the combination of Nakamura and Shimomura, to enable using the method of wafer rotation of Hashizume in the coating and cleaning step of the wafer bonding method of the combination of Nakamura and Shimomura, for the benefit of distributing water across the entire wafer surface and the benefit of simplifying manufacturing by utilizing parameters of a known two fluid cleaning step for removing foreign material from a wafer surface.
Re claim 2: The combination of Nakamura, Shimomura, and Hashizume teaches the method of claim 1, wherein the water has a resistance value ranging from about 0.5 MΩ·cm to about 18.3 MΩ·cm (Hashizume – para. 33|water used to coat and clean the wafer surface is deionized water (DIW); the resistivity value of deionized water used in wafer cleaning operations is inherently between 0.5 to 18 MΩ·cm (Wang et al. – CN 115945434 A), and "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists,” as per MPEP 2144.05(i)).
Re claim 3: The combination of Nakamura, Shimomura, and Hashizume teaches the method of claim 1, wherein the first rotational speed, the second rotational speed, the third rotational speed, and the fourth rotational speed are independently about 1500 rpm to about 3500 rpm (Hashizume – para. 37-38|Hashizume specifically discloses that the rotational speed of a wafer during the two fluid coating and cleaning with deionized water step is 500 to 2500 rpm, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”).
Re claim 4: The combination of Nakamura, Shimomura, and Hashizume teaches the method of claim 1, further comprising: before coating the first surface of the handle wafer, the second surface of the device wafer, or the combination thereof with the water, treating the first surface, the second surface, or the combination thereof with plasma (Shimomura - para. 143| water coating and cleaning step is performed after plasma activation step to remove dust and foreign organic material prior to bonding).
Re claim 6: The combination of Nakamura, Shimomura, and Hashizume teaches the method of claim 4, wherein the plasma comprises an oxygen plasma, a nitrogen plasma, an argon plasma, or combinations thereof (Nakamura – para. 34).
Re claim 7: The combination of Nakamura, Shimomura, and Hashizume teaches the method of claim 1, wherein coating the first surface of the handle wafer, the second surface of the device wafer, or the combination thereof with the water comprises: providing the water and a gas with a nozzle to spray the water onto the first surface, the second surface, or the combination thereof (Hashizume – para. 33).
Re claim 9: The combination of Nakamura, Shimomura, and Hashizume teaches the method of claim 1, wherein at least one of the handle wafer and the device wafer comprises a wafer body and an insulating layer, and the insulating layer covers the wafer body (Nakamura – para. 8: FIG. 1a, 1b: el. insulating film, bond wafer).
Re claim 10: The combination of Nakamura, Shimomura, and Hashizume teaches the method of claim 1, wherein bonding the first surface of the handle wafer and the second surface of the device wafer is performed at about 180 °C to about 1100 °C (Shimomura – para. 151|Shimomura specifically discloses a bonding temperature range of about 25°C to 400 °C, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”).
Re claim 11: The combination of Nakamura, Shimomura, and Hashizume teaches the method of claim 10, wherein bonding the first surface of the handle wafer and the second surface of the device wafer is performed at about 180 °C to about 600 °C (Shimomura – para. 151|Shimomura specifically discloses a bonding temperature range of about 25°C to 400 °C, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Shimomura and Hashizume as applied to claim 4 above, and further in view of Moriceau et al. (“Direct Wafer Bonding Surface Conditioning. In Handbook of Cleaning in Semiconductor Manufacturing,” pg. 519-525; hereinafter referred to as “Moriceau”).
Re claim 5: The combination of Nakamura, Shimomura, and Hashizume fails to teach the method of claim 4, wherein during treating the first surface of the handle wafer, the second surface of the device wafer, or the combination thereof with the plasma, a bombardment time of the plasma is from 15 seconds to 30 seconds.
In a similar field of endeavor, Moriceau teaches a method of wafer bonding including a plasma surface activation step preceding a water coating step (pg. 519-520). Moriceau further teaches a method of wafer bonding, wherein during treating the first surface of the handle wafer, the second surface of the device wafer, or the combination thereof with the plasma, a bombardment time of the plasma is from 15 seconds to 30 seconds (pg. 520: para. 3). Moriceau also teaches a benefit of a 30 second plasma treatment prior to wafer bonding is high bonding energies requiring only limited thermal annealing (pg. 520: para 3; pg. 521: FIG. 14.13).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Moriceau with the teachings of the combination of Nakamura, Shimomura, and Hashizume, to enable using the plasma treatment time of Moriceau in the plasma treatment step of the wafer bonding method of the combination of Nakamura, Shimomura, and Hashizume, for the benefit of simplifying manufacturing by using known process parameters for achieving high bonding energies requiring limited thermal annealing.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Shimomura and Hashizume as applied to claim 7 above, and further in view of Kanno et al. (US PGPub 20070141849 A1; hereinafter referred to as “Kanno”)
Re claim 8: The combination of Nakamura, Shimomura, and Hashizume fails to teach the method of claim 7, wherein when providing the water and the gas with the nozzle, a flow rate of the water is about 0.14 L/min to about 0.22 L/min, and a flow rate of the gas is about 40 L/min to about 75 L/min.
In a similar field of endeavor, Kanno teaches two fluid cleaning with pure deionized water of a wafer surface (abstract, para. 69-71). Kanno teaches when providing the water and the gas with the nozzle, a flow rate of the water is about 0.14 L/min to about 0.22 L/min, and a flow rate of the gas is about 40 L/min to about 75 L/min (para. 53, 55|Kanno specifically discloses a flow rate of wafer of 0.1 L/min to 0.2 L/min and a flow rate of gas of 10 L/min to 100 L/min, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Kanno also teaches benefits of the disclosed water and gas flow rates are sufficient atomization of liquid droplets along with improved cleaning performance and the prevention of particle re-deposition on the wafer surface.
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Kanno with the teachings of the combination of Nakamura, Shimomura, and Hashizume, to enable using the water and gas flow rates of Kanno in the two fluid cleaning step of the wafer bonding method of the combination of Nakamura, Shimomura, and Hashizume, for the benefits of sufficient atomization of liquid droplets, improved cleaning performance, and the prevention of particle re-deposition on the wafer surface.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Shimomura.
Re claim 12: Nakamura teaches a method of wafer bonding, comprising: receiving a handle wafer and a device wafer (para. 28| a bond wafer (device wafer) and a base wafer (handle wafer) are subjected to a bonding process to provide a bonded wafer); treating a first surface of the handle wafer, a second surface of the device wafer, or a combination thereof with plasma (para. 34); and bonding the first surface of the handle wafer and the second surface of the device wafer (FIG. 1d; para. 10). Nakamura fails to teach coating the first surface treated with the plasma, the second surface treated with the plasma, or a combination thereof with water.
In a similar field of endeavor, Shimomura teaches a method of bonding substrates comprising: receiving a handle substrate and a device substrate (FIG. 2A1, 2B1: el. 100, 120; para. 113, 114, 142| device substrate 100 and handle substrate 120 are received to be prepared for bonding); treating a first surface of the handle substrate, a second surface of the device substrate, or a combination thereof with plasma (para. 143); coating the first surface treated with the plasma, the second surface treated with the plasma, or a combination thereof with water (para. 143|two fluid cleaning, using pure water and nitrogen gas, is performed on at least one bonding surface to coat and clean the bonding surface after plasma activation of the bonding surface). Shimomura further teaches a benefit of coating the bonding surface with water using a two-fluid clean is to improve strength of the bond by removing dust such as organic material on the bonding surface (para. 143).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Nakamura and Shimomura to enable using the water coating and cleaning step of Shimomura in the wafer bonding method of Nakamura for the benefit of removing dust such as organic material on the bonding surface to improve bond strength.
Re claim 13: The combination of Nakamura and Shimomura teaches the method of claim 12, wherein the plasma comprises an oxygen plasma, a nitrogen plasma, an argon plasma, or combinations thereof (Nakamura – para. 34).
Re claim 14: The combination of Nakamura and Shimomura teaches the method of claim 12, wherein bonding the first surface of the handle wafer and the second surface of the device wafer is performed at about 180 °C to about 1100 °C (Shimomura – para. 151|Shimomura specifically discloses a bonding temperature range of about 25°C to 400 °C, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”).
Re claim 15: The combination of Nakamura and Shimomura teaches the method of claim 12, wherein at least one of the handle wafer and the device wafer comprises a wafer body and an insulating layer, and the insulating layer covers the wafer body (Nakamura – para. 8: FIG. 1a, 1b: el. insulating film, bond wafer).
26. Claims 16, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Shimomura as applied to claim 12 above, and further in view of Hashizume.
Re claim 16: The combination of Nakamura and Shimomura teaches the method of claim 12. The combination of Nakamura and Shimomura fails to teach the method of claim 12, wherein the water has a resistance value ranging from about 0.5 MΩ·cm to about 18.3 MΩ·cm.
In a similar field of endeavor, Hashizume teaches a method of two fluid cleaning with pure deionized water for the benefit of removing foreign material from a wafer surface (para. 33). Hashizume teaches a method of coating a wafer surface with water, wherein the water has a resistance value ranging from about 0.5 MΩ·cm to about 18.3 MΩ·cm (Hashizume – para. 33|water used to coat and clean the wafer surface is deionized water (DIW); the resistivity value of deionized water used in wafer cleaning operations is inherently between 0.5 to 18 MΩ·cm (Wang et al. – CN 115945434 A), and "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists,” as per MPEP 2144.05(i)).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings Hashizume and the teachings of the combination of Nakamura and Shimomura, to enable using the method of two fluid cleaning with deionized water of Hashizume in the coating and cleaning step of the wafer bonding method of the combination of Nakamura and Shimomura, for the benefit of simplifying manufacturing by utilizing parameters of a known two fluid cleaning step for removing foreign material from a wafer surface.
Re claim 17: The combination of Nakamura, Shimomura, and Hashizume teaches the method of claim 12, wherein the water does not comprise ammonia, a chelating agent, a surfactant, or combinations thereof (Hashizume – para. 33|deionized water is used as the water).
Re claim 19: The combination of Nakamura, Shimomura, and Hashizume teaches the method of claim 12, wherein coating the first surface treated with the plasma, the second surface treated with the plasma, or the combination thereof with the water comprises: providing the water and a gas with a nozzle to spray the water onto the first surface, the second surface, or the combination thereof (Hashizume – para. 33).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Shimomura as applied to claim 12 above, and further in view of Moriceau.
Re claim 18: The combination of Nakamura and Shimomura fails to disclose the method of claim 12, wherein during treating the first surface of the handle wafer, the second surface of the device wafer, or the combination thereof with the plasma, a bombardment time of the plasma is from 15 seconds to 30 seconds.
In a similar field of endeavor, Moriceau teaches a method of wafer bonding including a plasma surface activation step preceding a water coating step (pg. 519-520). Moriceau teaches a method of wafer bonding, wherein during treating the first surface of the handle wafer, the second surface of the device wafer, or the combination thereof with the plasma, a bombardment time of the plasma is from 15 seconds to 30 seconds (pg. 520: para. 3). Moriceau also teaches a benefit of a 30 second plasma treatment prior to wafer bonding is high bonding energies requiring only limited thermal annealing (pg. 520: para 3; pg. 521: FIG. 14.13).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Moriceau with the teachings of the combination of Nakamura and Shimomura to enable using the plasma treatment time of Moriceau in the plasma treatment step of the wafer bonding method of the combination of Nakamura and Shimomura, for the benefit of simplifying manufacturing by using known process parameters for achieving high bonding energies requiring limited thermal annealing.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura in view of Shimomura as applied to claim 12 above, and further in view of Plach et al. (US PGPub 20150165752 A1; hereinafter referred to as “Plach”)
Re claim 20: The combination of Nakamura and Shimomura fails to disclose the method of claim 12, further comprising: before treating the first surface of the handle wafer, the second surface of the device wafer, or the combination thereof with the plasma, generating the plasma by an upper electrode and a lower electrode, wherein the upper electrode and the lower electrode are respectively connected to radio frequency power supplies with a frequency of about 40 kHz to about 400 kHz.
In a similar field of endeavor, Plach teaches a method of wafer bonding including a plasma surface activation step. Plach teaches a method of wafer bonding, further comprising: before treating the first surface of the handle wafer, the second surface of the device wafer, or the combination thereof with the plasma, generating the plasma by an upper electrode and a lower electrode (FIG. 9: el. 21, 22), wherein the upper electrode and the lower electrode are respectively connected to radio frequency power supplies with a frequency of about 40 kHz to about 400 kHz (FIG. 9: el. 21, 22; para. 100, 132-133| Plach specifically discloses a frequency of 250 kHz to 550 kHz for an upper electrode and a frequency of 15kHz to 55kHz for a lower electrode, and as per MPEP 2144.05(i), "in the case where the claimed ranges ‘overlap or lie inside ranges disclosed by the prior art’ a prima facie case of obviousness exists”). Plach also teaches benefits of plasma activation with this frequency range is a uniform depth distribution of ions on the treated surface, a smoothing effect, and improved hydrophilicity of the treated surface (para. 100, 132-133).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Plach with the teachings of the combination of Nakamura and Shimomura to enable using the plasma treatment frequency of Plach in the plasma treatment step of the wafer bonding method of the combination of Nakamura and Shimomura, for the benefits of a smoothing effect, improved hydrophilicity, and a uniform depth distribution of ions on the treated surface.
Conclusion
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/D.G./ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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