DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 07/21/2026 has been accepted and entered. Claim 1-19 remain pending in this application. Applicant’s amendments to Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed on 04/28/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-9, 11-12, 15, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 20240136202 A1-Hung02) in view of Hsieh et al. (US20200312897A1-Hsieh97).
Regarding claim 1, Hung02 discloses a semiconductor package (semiconductor package 100a with CMOS sensor 20-Examiner’s annotated Fig 13, [0030] L1-8) comprising:
a package substrate with top and bottom major package substrate surfaces (Package substrate 10 with top and bottom major substrate surfaces 101/102-Examiner’s annotated Fig 13, [0028] L8-9),
wherein the top major package substrate surface (101) includes
a die region with a die pad (Die region with die pad-Examiner's annotated Fig 13, [0030] L1-4) and
a non-die region (Left/Right regions as indicated by the Left/Right dashed line rectangles-Examiner's annotated Fig 13),
the non-die region includes package bond pads (Non-die regions including package bond pads 11-Examiner's annotated Fig 13), and
the bottom major package substrate surface includes package contact pads (Bottom major package substrate surface 102 including package contact pads 13-Examiner's annotated Fig 13, [0031] L1-3),
wherein the package contact pads on the bottom major package substrate surface are electrically connected to the respective package bond pads on the top major package substrate surface (package contact pads 13 on the bottom major package substrate surface 102 in direct contact with the conductive substrate 10, so being electrically connected to the respective package bond pads 11 on the top major package substrate surface 101-Examiner's annotated Fig 13, [0030] L11-12);
a sensor die having active and inactive major die surfaces (sensor die 20 having a photosensitive portion at a top surface thereof so having active/top and inactive/bottom major die surfaces-Examiner's annotated Fig 13, {0030] L1-6),
wherein the active major die surface (top surface) includes
a sensor region with a sensor (Sensor region with sensor as represented by the half circles-Examiner's annotated Fig 13),
a non-sensor region with die bond pads (Non-sensor region with die bond pads 21-Examiner's annotated Fig 13) and
a cover adhesive region surrounding the sensor region (Cover adhesive region 40 surrounding the sensor region as indicated by the central dashed line rectangle-[0033] L1-7, Examiner's annotated Fig 13), and
the inactive major die surface is attached to the die pad (inactive/bottom major die surface 102 attached to die pad-Examiner's annotated Fig 13, [0030] L1-12);
wire bonds connecting the die bond pads on the active major die surface and the package bond pads on the top major package substrate surface (Wire bonds 30 on each side, connecting die bond pads 21 on the active/top major die surface and the package bond pad 11 on the top major die surface 101-Examiner's annotated Fig 13);
a transparent cover disposed over the sensor die covering the sensor region (Transparent cover 50 disposed over sensor die 20, covering the sensor region-Examiner's annotated Fig 13, [0035] L1-4),
wherein the transparent cover is attached by a cover adhesive on the cover adhesive region of the active major die surface (transparent cover 50 adhering to cover so attached by a cover adhesive on the cover adhesive region 40 of the active/top major die 20 surface-Examiner's annotated Fig 13, [0035] L1-4),
wherein the transparent cover forms a sealed cavity between the transparent cover and the sensor (transparent cover 50 forming a sealed cavity between the transparent cover 50 and the sensor 20-Examiner's annotated Fig 13);
a package encapsulation (Package encapsulation 70-Examiner's annotated Fig 13),
the package encapsulation encapsulates the package substrate, the wire bonds and side cover surfaces and outer sides of the cover adhesive (Package encapsulation 70, encapsulating package substrate 10, wire bonds 30, and side cover surface and outer sides of cover adhesive 40-Examiner's annotated Fig 13); and
an opaque layer disposed on a top surface of the package encapsulation (Black so opaque layer added on the transparent cover 50 to prevent flare issue in addition of top layer of Cover adhesive region 40 which is black so opaque-Examiner's annotated Fig 13, [0004] L10-13, [0033] L1-7).
Hung02 does not disclose a semiconductor package
wherein the opaque layer obscures the wire bonds within the package encapsulation to reduce reflectance to improve sensor performance.
Hsieh97 teaches a semiconductor package (Title, [0007] L1-15)
wherein the opaque layer obscures the wire bonds within the package encapsulation to reduce reflectance to improve sensor performance (Non-transparent so opaque layer 210 added on the transparent cover 206 and on the package encapsulation 230 to prevent flare issue-[0035] L1-8, Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Hung02, as taught by Hsieh97 for the purpose of reducing or blocking flare within the image sensor package (Hsieh97: [0008]).
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Regarding claim 2, Hung02 and Hsieh97 combination discloses all the elements of claim 1, as noted above.
Hsieh97 further teaches a semiconductor package
wherein the opaque layer prevents reflectance (Non-transparent so opaque layer 210 added on the transparent cover 206 and on the package encapsulation 230 so above the wire bonds 222 so obscuring the wire bonds 222 to reduce/eliminate flare issue so to prevent reflectance-[0035] L1-8, Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Hung02, as taught by Hsieh97 for the purpose of reducing or blocking flare within the image sensor package (Hsieh97: [0008]).
Regarding claim 3, Hung02 and Hsieh97 combination discloses all the elements of claim 1, as noted above.
Hsieh97 further teaches a semiconductor package
wherein the opaque layer extends beyond the package encapsulation and covers a peripheral portion of the transparent cover to form a cover opaque region (Non-transparent so opaque layer 210 added on the transparent cover 206 and on the package encapsulation 230 to prevent flare issue-[0035] L1-8, Examiner's annotated Fig 2),
wherein the cover opaque region enables the sensor to sense while reducing flaring and scattering to enhance the sensor performance (Non-transparent so opaque layer 210 added on the transparent cover 206 sides and leaving a central open region above the sensor 204 so enabling the sensor 204 to sense-[0033] L1-12, Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Hung02, as taught by Hsieh97 for the purpose of reducing or blocking flare within the image sensor package (Hsieh97: [0008]).
Regarding claim 4, Hung02 and Hsieh97 combination discloses all the elements of claim 3, as noted above.
Hsieh97 further teaches a semiconductor package
wherein the opaque layer prevents reflectance (Non-transparent so opaque layer 210 added on the transparent cover 206 and on the package encapsulation 230 so above the wire bonds 222 so obscuring the wire bonds 222 to reduce/eliminate flare issue so to prevent reflectance-[0035] L1-8, Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Hung02, as taught by Hsieh97 for the purpose of reducing or blocking flare within the image sensor package (Hsieh97: [0008]).
Regarding claim 5, Hung02 and Hsieh97 combination discloses all the elements of claim 3, as noted above.
Hsieh97 further teaches a semiconductor package
wherein the opaque layer in the opaque region on the transparent cover prevents flaring and scattering to further enhance sensor performance. (Non-transparent so opaque layer 210 added on the transparent cover 206 and on the package encapsulation 230 reducing flare issue so preventing flaring and scattering to further enhance sensor performance-[0035] L1-8, Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Hung02, as taught by Hsieh97 for the purpose of reducing or blocking flare within the image sensor package (Hsieh97: [0008]).
Regarding claim 7, Hung02 and Hsieh97 combination discloses all the elements of claim 1, as noted above.
Hsieh97 further teaches a semiconductor package
wherein the package encapsulation comprises an epoxy mold compound (Package encapsulation 130 comprising a molding compound including epoxy so an epoxy molding compound-[0032] L1-11, Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Hung02, as taught by Hsieh97 for the purpose of reducing or blocking flare within the image sensor package (Hsieh97: [0008]).
Regarding claim 8, Hung02 and Hsieh97 combination discloses all the elements of claim 1, as noted above.
Hung02 further discloses a semiconductor package
wherein the sensor die comprises an image sensor die (sensor die 20 comprising image sensor-[0030]L4-6).
Regarding claim 9, Hung02 and Hsieh97 combination discloses all the elements of claim 1, as noted above.
Hung02 further discloses a semiconductor package
wherein the transparent cover comprises a glass cover (transparent cover 50being a transparent glass-[0035]L1-4).
Regarding claim 11, Hung02 discloses a method for forming a semiconductor package (method for forming package 100a with CMOS sensor 20-Examiner’s annotated Fig 13, [0030] L1-8, Fig1):
providing a package substrate with top and bottom major package substrate surfaces (Providing Package substrate 10 with top and bottom major substrate surfaces 101/102-Step S10 of Fig 1, Examiner’s annotated Fig 13, [0028] L8-9),
wherein the top major package substrate surface (101) includes
a die region with a die pad (Die region with die pad-Examiner's annotated Fig 13, [0030] L1-4) and
a non-die region (Left/Right regions as indicated by the Left/Right dashed line rectangles-Examiner's annotated Fig 13),
the non-die region includes package bond pads (Non-die regions including package bond pads 11-Examiner's annotated Fig 13), and
the bottom major package substrate surface includes package contact pads (Bottom major package substrate surface 102 including package contact pads 13-Examiner's annotated Fig 13, [0031] L1-3),
wherein the package contact pads on the bottom major package substrate surface are electrically connected to the respective package bond pads on the top major package substrate surface (package contact pads 13 on the bottom major package substrate surface 102 in direct contact with the conductive substrate 10, so being electrically connected to the respective package bond pads 11 on the top major package substrate surface 101-Examiner's annotated Fig 13, [0030] L11-12);
providing a sensor die having active and inactive major die surfaces (Providing a sensor die 20 having a photosensitive portion at a top surface thereof so having active/top and inactive/bottom major die surfaces-Examiner's annotated Fig 13, {0030] L1-6, Step S30 of Fig 1),
wherein the active major die surface (top surface) includes
a sensor region with a sensor (Sensor region with sensor as represented by the half circles-Examiner's annotated Fig 13),
a non-sensor region with die bond pads (Non-sensor region with die bond pads 21-Examiner's annotated Fig 13) and
a cover adhesive region surrounding the sensor region (Cover adhesive region 40 surrounding the sensor region as indicated by the central dashed line rectangle-[0033] L1-7, Examiner's annotated Fig 13), and
attaching the inactive major die surface of the die to the die pad (attaching inactive/bottom major die surface 102 attached to die pad-Examiner's annotated Fig 13, [0030] L1-12, Step S30 of Fig 1);
performing wire bonding to electrically connect the die bond pads on the active major die surface and the package bond pads on the top major package substrate surface (Performing Wire bonding and forming wire bonds 30 on each side, connecting die bond pads 21 on the active/top major die surface and the package bond pad 11 on the top major die surface 101-Examiner's annotated Fig 13, Step 40 of Fig 1);
attaching a transparent cover over the sensor die covering the sensor region by a cover adhesive on the cover adhesive region of the active major die surface (attaching Transparent cover 50 disposed over sensor die 20, covering the sensor region-Examiner's annotated Fig 13, [0035] L1-4, Step S50 of Fig 1),
wherein the transparent cover forms a sealed cavity between the transparent cover and the sensor (transparent cover 50 forming a sealed cavity between the transparent cover 50 and the sensor 20-Examiner's annotated Fig 13);
encapsulating the package with a package encapsulation (Encapsulating the package with Package encapsulation 70-Step 70 of Fig 1, [0037]),
the package encapsulation encapsulates the package substrate, the wire bonds and side cover surfaces and outer sides of the cover adhesive (Package encapsulation 70, encapsulating package substrate 10, wire bonds 30, and side cover surface and outer sides of cover adhesive 40-Examiner's annotated Fig 13).
Hung02 does not disclose a method for forming a semiconductor package comprising
forming an opaque layer on a top surface of the package encapsulation,
wherein the opaque layer obscures the wire bonds within the package encapsulation to reduce reflectance to improve sensor performance.
Hsieh97 teaches a method for forming a semiconductor package (Title, [0007] L1-15, [0008], Fig 9A, Fig 9B) comprising
forming an opaque layer on a top surface of the package encapsulation (Forming non-transparent so opaque layer 210 added on the transparent cover 206 and on the package encapsulation 230-Step 958 of Fig 9B),
wherein the opaque layer obscures the wire bonds within the package encapsulation to reduce reflectance to improve sensor performance (Non-transparent so opaque layer 210 added on the transparent cover 206 and on the package encapsulation 230 to prevent flare issue-[0035] L1-8, Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for forming a semiconductor package of Hung02, as taught by Hsieh97 for the purpose of reducing or blocking flare within the image sensor package (Hsieh97: [0008]).
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Regarding claim 12, Hung02 and Hsieh97 combination discloses all the elements of claim 11, as noted above.
Hsieh97 further teaches a method for forming a semiconductor package
wherein the opaque layer prevents reflectance (Non-transparent so opaque layer 210 added on the transparent cover 206 and on the package encapsulation 230 so above the wire bonds 222 so obscuring the wire bonds 222 to reduce/eliminate flare issue so to prevent reflectance-[0035] L1-8, Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for forming a semiconductor package of Hung02, as taught by Hsieh97 for the purpose of reducing or blocking flare within the image sensor package (Hsieh97: [0008]).
Regarding claim 15, Hung02 and Hsieh97 combination discloses all the elements of claim 11, as noted above.
Hsieh97 further teaches a method for forming a semiconductor package
wherein the opaque layer extends beyond the package encapsulation and covers a peripheral portion of the transparent cover to form a cover opaque region (Non-transparent so opaque layer 210 added on the transparent cover 206 and on the package encapsulation 230 to prevent flare issue-[0035] L1-8, Examiner's annotated Fig 2),
wherein the cover opaque region enables the sensor to sense while reducing flaring and scattering to enhance the sensor performance (Non-transparent so opaque layer 210 added on the transparent cover 206 sides and leaving a central open region above the sensor 204 so enabling the sensor 204 to sense-[0033] L1-12, Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for forming a semiconductor package of Hung02, as taught by Hsieh97 for the purpose of reducing or blocking flare within the image sensor package (Hsieh97: [0008]).
Regarding claim 18, Hung02 discloses a semiconductor package (semiconductor package 100a with CMOS sensor 20-Examiner’s annotated Fig 13, [0030] L1-8) comprising:
a package substrate with top and bottom major package substrate surfaces (Package substrate 10 with top and bottom major substrate surfaces 101/102-Examiner’s annotated Fig 13, [0028] L8-9),
wherein the top major package substrate surface (101) includes
a die region with a die pad (Die region with die pad-Examiner's annotated Fig 13, [0030] L1-4) and
a non-die region (Left/Right regions as indicated by the Left/Right dashed line rectangles-Examiner's annotated Fig 13),
the non-die region includes package bond pads (Non-die regions including package bond pads 11-Examiner's annotated Fig 13), and
the bottom major package substrate surface includes package contact pads (Bottom major package substrate surface 102 including package contact pads 13-Examiner's annotated Fig 13, [0031] L1-3),
wherein the package contact pads on the bottom major package substrate surface are electrically connected to the respective package bond pads on the top major package substrate surface (package contact pads 13 on the bottom major package substrate surface 102 in direct contact with the conductive substrate 10, so being electrically connected to the respective package bond pads 11 on the top major package substrate surface 101-Examiner's annotated Fig 13, [0030] L11-12);
a sensor die having active and inactive major die surfaces (sensor die 20 having a photosensitive portion at a top surface thereof so having active/top and inactive/bottom major die surfaces-Examiner's annotated Fig 13, {0030] L1-6),
wherein the active major die surface (top surface) includes
a sensor region with a sensor (Sensor region with sensor as represented by the half circles-Examiner's annotated Fig 13),
a non-sensor region with die bond pads (Non-sensor region with die bond pads 21-Examiner's annotated Fig 13) and
a cover adhesive region surrounding the sensor region (Cover adhesive region 40 surrounding the sensor region as indicated by the central dashed line rectangle-[0033] L1-7, Examiner's annotated Fig 13), and
the inactive major die surface is attached to the die pad (inactive/bottom major die surface 102 attached to die pad-Examiner's annotated Fig 13, [0030] L1-12);
wire bonds connecting the die bond pads on the active major die surface and the package bond pads on the top major package substrate surface (Wire bonds 30 on each side, connecting die bond pads 21 on the active/top major die surface and the package bond pad 11 on the top major die surface 101-Examiner's annotated Fig 13); a transparent cover disposed over the sensor die covering the sensor region (Transparent cover 50 disposed over sensor die 20, covering the sensor region-Examiner's annotated Fig 13, [0035] L1-4),
wherein the transparent cover is attached by a cover adhesive on the cover adhesive region of the active major die surface (transparent cover 50 adhering to cover so attached by a cover adhesive on the cover adhesive region 40 of the active/top major die 20 surface-Examiner's annotated Fig 13, [0035] L1-4),
wherein the transparent cover forms a sealed cavity between the transparent cover and the sensor (transparent cover 50 forming a sealed cavity between the transparent cover 50 and the sensor 20-Examiner's annotated Fig 13);
a package encapsulation (Package encapsulation 70-Examiner's annotated Fig 13),
the package encapsulation encapsulates the package substrate, the wire bonds and side cover surfaces and outer sides of the cover adhesive (Package encapsulation 70, encapsulating package substrate 10, wire bonds 30, and side cover surface and outer sides of cover adhesive 40-Examiner's annotated Fig 13); and
an opaque layer disposed on a top surface of the package encapsulation (Black so opaque layer added on the transparent cover 50 to prevent flare issue in addition of top layer of Cover adhesive region 40 which is black so opaque-Examiner's annotated Fig 13, [0004] L10-13, [0033] L1-7).
Hung02 does not disclose a semiconductor package
wherein the opaque layer obscures the wire bonds within the package encapsulation to reduce reflectance to improve sensor performance.
Hsieh97 teaches a semiconductor package (Title, [0007] L1-15)
wherein the opaque layer obscures the wire bonds within the package encapsulation to reduce reflectance to improve sensor performance (Non-transparent so opaque layer 210 added on the transparent cover 206 and on the package encapsulation 230 to prevent flare issue-[0035] L1-8, Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Hung02, as taught by Hsieh97 for the purpose of reducing or blocking flare within the image sensor package (Hsieh97: [0008]).
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Claim(s) 6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 20240136202 A1-Hung02) in view of Hsieh et al. (US20200312897A1-Hsieh97), and further in view of Dong et al. (US 20120032216 A1-Dong16).
Regarding claim 6, Hung02 and Hsieh97 combination discloses all the elements of claim 1, as noted above.
Hung02 and Hsieh97 combination does not teach a semiconductor package
wherein the opaque layer comprises black ink
Dong16 teaches a semiconductor package
wherein the opaque layer comprises black ink (opaque layer 338 comprising black ink-[0060] L8-10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor package of Hung02 in view of Hsieh97, as taught by Dong16 for the purpose of making an opaque layer (Dong16: [0060]).
Regarding claim 19, Hung02 and Hsieh97 combination discloses all the elements of claim 18, as noted above.
Hung02 and Hsieh97 combination does not teach a semiconductor package
wherein the opaque layer comprises black ink
Dong16 teaches a semiconductor package
wherein the opaque layer comprises black ink (opaque layer 338 comprising black ink-[0060] L8-10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor package of Hung02 in view of Hsieh97, as taught by Dong16 for the purpose of making an opaque layer (Dong16: [0060]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 20240136202 A1-Hung02) in view of Hsieh et al. (US20200312897A1-Hsieh97), and further in view of Punzalan et al. (US20220093664A1-Punzalan64).
Regarding claim 10, Hung02 and Hsieh97 combination discloses all the elements of claim 1, as noted above.
Hung02 and Hsieh97 combination does not disclose a semiconductor package
wherein the die bond pads are disposed within the cover adhesive region of the active die surface.
Punzalan64 teaches a semiconductor package
wherein the die bond pads are disposed within the cover adhesive region of the active die surface (Die bond pads 132 disposed within the cover adhesive region 143 of the active die surface 130a-Examiner's annotated Fig 1b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor package of Hung02 in view of Hsieh97, as taught by Punzalan64 for the purpose of improving the package reliability and performance by preventing contaminations on undesired areas of the package during packaging (Punzalan64: [0005]).
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Claim(s) 13-14 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 20240136202 A1-Hung02) in view of Hsieh et al. (US20200312897A1-Hsieh97), and further in view of Nimishura et al. (US 20210223512 A1-Nimishura12).
Regarding claim 13, Hung02 and Hsieh97 combination discloses all the elements of claim 11, as noted above.
Hung02 and Hsieh97 combination does not teach a method for forming a semiconductor package
wherein forming the opaque layer comprises forming a black ink layer.
Nimishura12 teaches a method for forming a semiconductor package
wherein forming the opaque layer comprises forming a black ink layer (black mask/opaque layer 321 provided by ink jet so by forming a black ink layer-[0272] L1-14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor package of Hung02 in view of Hsieh97, as taught by Nimishura12 for the purpose of making an opaque/black mask when having a surface with low flatness (Nimishura12 : [0272]).
Regarding claim 14, Hung02 and Hsieh97 combination discloses all the elements of claim 13, as noted above.
Hung02 and Hsieh97 combination does not teach a method for forming a semiconductor package
wherein forming the black ink layer comprises an ink jet process.
Nimishura12 teaches a method for forming a semiconductor package
wherein forming the black ink layer comprises an ink jet process (black mask/opaque layer 321 provided by ink jet so comprising an ink jet process-[0272] L1-14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor package of Hung02 in view of Hsieh97, as taught by Nimishura12 for the purpose of making an opaque/black mask when having a surface with low flatness (Nimishura12 : [0272]).
Regarding claim 16, Hung02 and Hsieh97 combination discloses all the elements of claim 15, as noted above.
Hung02 and Hsieh97 combination does not teach a method for forming a semiconductor package
wherein forming the opaque layer comprises forming a black ink layer.
Nimishura12 teaches a method for forming a semiconductor package
wherein forming the opaque layer comprises forming a black ink layer (black mask/opaque layer 321 provided by ink jet so by forming a black ink layer-[0272] L1-14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor package of Hung02 in view of Hsieh97, as taught by Nimishura12 for the purpose of making an opaque/black mask when having a surface with low flatness (Nimishura12 : [0272]).
Regarding claim 17, Hung02, Hsieh97, and Nimishura12 combination discloses all the elements of claim 14, as noted above.
Hsieh97 further teaches a method for forming a semiconductor package
Wherein forming the opaque layer prevents reflectance (forming Non-transparent so opaque layer 210 added on the transparent cover 206 and on the package encapsulation 230 so above the wire bonds 222 so obscuring the wire bonds 222 to reduce/eliminate flare issue so to prevent reflectance-[0035] L1-8, Examiner's annotated Fig 2, Step 958 of Fig 9B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for forming a semiconductor package of Hung02, as taught by Hsieh97 for the purpose of reducing or blocking flare within the image sensor package (Hsieh97: [0008]).
Response to Arguments
Applicant’s arguments see pages 8-12 of Remarks, filed on 07/21/2026 with respect to the 35 U.S.C. 102(a)(2) rejection of claims 1-9 and 11-19 have been fully considered and are persuasive. The 35 U.S.C. 102(a)(2) rejection of claims 1-9 and 11-19 has been withdrawn.
Applicant’s arguments see pages 8-12 of Remarks, filed on 07/21/2026 with respect to the 35 U.S.C. 103 rejection of claim 10 have been fully considered and are persuasive. The 35 U.S.C. 103 rejection of claim 1-9 and 11-19 has been withdrawn.
Claims 1, 11, and 18 have been amended and have been broaden by canceling the claim limitation “and a cover adhesive region surrounding the die region”. Therefore, a new ground of rejection is necessitated by applicant’s amendment to the claims (See MPEP 706.07(a)). The applicability of the reference to the amended elements is discussed in the claim rejections above.
Therefore, claim(s) 1-5, 7-9, 11-12, 15, 18 stand rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 20240136202 A1-Hung02) in view of Hsieh et al. (US20200312897A1-Hsieh97).
Therefore, claim(s) 6 and 19 stand rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 20240136202 A1-Hung02) in view of Hsieh et al. (US20200312897A1-Hsieh97), and further in view of Dong et al. (US 20120032216 A1-Dong16).
Therefore, claim(s) 10 stand rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 20240136202 A1-Hung02) in view of Hsieh et al. (US20200312897A1-Hsieh97), and further in view of Punzalan et al. (US20220093664A1-Punzalan64).
Therefore, claim(s) 13-14 and 16-17 stand rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 20240136202 A1-Hung02) in view of Hsieh et al. (US20200312897A1-Hsieh97), and further in view of Nimishura et al. (US 20210223512 A1-Nimishura12).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 10/07/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
