Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks/Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot in view of the new grounds of rejection.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show
every feature of the invention specified in the claims. Therefore, “a second conductive path that is electrically isolated from the first conductive path” in claim 1, lines 14-15, “a second conductive path that includes the first wire and that is electrically isolated from the first conductive path” in claim 11, lines 8-9, “the first wire and the at least one second wire and is electrically isolated from the first conductive path” in claim 17, lines 21-23 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 1 lacks antecedent basis for “a second conductive path” (line 14) and “first conductive path” (line 13).
Claim 11 lacks antecedent basis for “a second conductive path” (line 8) and “first conductive path” (line 9).
Claim 17 lacks antecedent basis for “a second conductive path” (line 21) and “first conductive path” (line 22).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites (lines 13-14) “a second conductive path that is electrically isolated from the first conductive path.” It does not appear to have support for first conductive path being isolated from second conductive path. The first wire (fig. 2A item 271) and second wire (Fig 2a. item 272) are not electrically isolated.
Claims 2-10 are rejected for the reasons above due to dependence on claim 1.
Claim 11 recites (lines 8-9) “a second conductive path that includes the first wire and that is electrically isolated from the first conductive path;”. It does not appear to have support for first conductive path being isolated from second conductive path. The first wire (fig. 2A item 271) and second wire (Fig 2a. item 272) are not electrically isolated.
Claims 11-16 are rejected for the reasons above due to dependence on claim 11.
Claim 17 recites (lines 19-21) “a second conductive path that includes the first wire and the at least one second wire and is electrically isolated from the first conductive path;”. It does not appear to have support for first conductive path being isolated from second conductive path. The first wire (fig. 2A item 271) and second wire (Fig 2a. item 272) are not electrically isolated.
Claims 18-20 are rejected for the reasons above due to dependence on claim 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 5-7, 9-10 are rejected under 35 U.S.C. 103(a) as being unpatentable over Lund et al. (US 5804979 A) in view of LI et al. (US 20170074951 A1).
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Regarding to claim 1, Lund discloses a circuit for detecting via degradation, comprising:
a current source (Fig. 1-3 Item 10 or 22 discloses a conductor 10 capable of conducting electrical current in Col3 Lines 0019-0067) configured to deliver a constant current supply to a plurality of conductive vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe 12 & 16 along the length of the conductor, with adjacent source and sense leads making electrical contact with the conductor 10 in Col3 Lines 0019-0067) of a device under testing (Fig. 1-3);
a plurality of switches ((Fig. 1-3 Item 20a & 20b] in Col3 Lines 0019-0067) configured to connect the current source (Fig. 1-3 Item 10 or 22 in Col3 Lines 0019-0067) to the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); and
an analog-to-digital converter (ADC) (Fig. 1-3 Item 28 voltmeter includes an “ADC”] in Col3 Lines 0019-0067) configured to be connected to the plurality of vias (Fig. 1-3 Item 12 & 16 in Col3 Lines 0019-0067); by the plurality of switches ((Fig. 1-3 Item 20a & 20b]) through a first wire ((Fig. 1-3 Item 20c discloses input to adc in Col3 Lines 0019-0067), wherein the first wire ((Fig. 1-3 Item 20c ) is connected to a first input of the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC”] in Col3 Lines 0019-0067)
wherein the plurality of switches ((Fig. 1-3 Item 20a & 20b] in Col3 Lines 0019-0067) are configured to connect one via of the plurality of vias (Fig. 1-3 Item 12 & 16 in Col3 Lines 0019-0067) at a time to the current source and to the first wire; and
wherein the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) is configured to output a signal (Fig. 1-3 Item 28 voltmeter includes an “ADC” output signal] in Col3 Lines 0019-0067) that represents the resistance of a via connected to the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC”] in Col3 Lines 0019-0067) and the current source (Fig. 1-3 Item 10 or 22).
wherein the current source (Fig. 1-3 Item 10 or 22) is connected to the via (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067) through a first conductive path and the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC”] in Col3 Lines 0019-0067) is connected to the via through a second conductive ((Fig. 1-3 Item 20a & 20b] in Col3 Lines 0019-0067).
Lund does not explicitly teach a second conductive path that is electrically isolated from the first conductive path.
However, LI teaches a second conductive path that is electrically isolated from the first conductive path. (Fig. 1-2 discloses the conductive wire and to electrically isolate the conductive wire from the portion of the first conductive layer in Paragraph [0012])
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify the voltage drop measured by a voltmeter and the resistance of the segment in Lund by substituting a second conductive path that is electrically isolated from the first conductive path by LI to accurately measure electrically isolated first and second conductive wires in abstract.
Regarding to claim 5, Lund discloses the circuit of claim 1, further comprising
a plurality of second wires connected to the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); in a one-to-one correspondence; and
a plurality of return vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); in a one-to-one correspondence with the plurality of second wires and the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067);
Regarding to claim 6, Lund discloses the circuit of claim 1, further comprising a second wire connected to each of the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); wherein the second wire is configured to connect the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); to a second input of the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067)
Regarding to claim 7, Lund discloses the circuit of claim 1, wherein the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) comprises a second input that is connected to a reference voltage (Fig. 1-3 Item 28 the voltmeter 28 and coupled to a microprocessor 30 which stores Von and Voff. in Col3 Lines 0019-0067).
Regarding to claim 9, Lund discloses the circuit of claim 1, further comprising a digital controller (Fig. 1-3 Item 30 the voltmeter 28 and coupled to a microprocessor 30 which stores Von and Voff. in Col3 Lines 0019-0067)
wherein the digital controller (Fig. 1-3 Item 30 the voltmeter 28 and coupled to a microprocessor 30 which stores Von and Voff. in Col3 Lines 0019-0067) is configured to control the plurality of switches ((Fig. 1-3 Item 20a & 20b] in Col3 Lines 0019-0067) to connect the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); to the current source (Fig. 1-3 Item 10 or 22 discloses a conductor 10 capable of conducting electrical current in Col3 Lines 0019-0067) and the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) in a pre-determined order.
Regarding to claim 10, Lund discloses the circuit of claim 1, wherein the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) comprises a comparator (Fig. 1-3 Item 28 & 30 the voltmeter 28 and coupled to a microprocessor 30 which stores Von and Voff. in Col3 Lines 0019-0067)
Claim 2-4, 8,11-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Lund et al. (US 5804979 A) in view of LI et al. (US 20170074951 A1) in view of WOO et al. (US 20170059648 A1).
Regarding to claim 2, Lund discloses the circuit of claim 1,
Lund does not explicitly teach wherein the plurality of vias comprises a plurality of through-silicon-vias (TSVs).
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However, WOO teaches wherein the plurality of vias comprises a plurality of through-silicon-vias (TSVs). (Fig. 1-6 Item 90a discloses the TSV via unit 90 for testing a signal transmission state of each TSV in the TSV unit 90 in Paragraph [0040])
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify the voltage drop measured by a voltmeter and the resistance of the segment in Lund by substituting semiconductor chips are electrically connected through one or more through-silicon vias (TSVs) by WOO to control a test operation for testing the signal transmission state of each TSV in Paragraph [0047]).
Regarding to claim 3, Lund discloses the circuit of claim 1.
Lund does not explicitly teach wherein the plurality of vias comprises a plurality of super power rails (SPRs).
However, WOO teaches wherein the plurality of vias comprises a plurality of super power rails (SPRs) (Fig. 1-6 Item 90a discloses the SPRs unit 90. When the test controller 120 receives a power-on signal (e.g., from an external source) for operating the semiconductor apparatus 10 in Paragraph [0027])
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify the voltage drop measured by a voltmeter and the resistance of the segment in Lund by substituting semiconductor chips are electrically connected through one or more through-silicon vias (TSVs) by WOO to control a test operation for testing the signal transmission state of each TSV in Paragraph [0047]).
Regarding to claim 4, Lund discloses the circuit of claim 1,
Lund does not explicitly teach wherein the plurality of vias comprises both TSVs and SPRs.
However, WOO teaches wherein the plurality of vias comprises both TSVs (Fig. 1-6 Item 90a discloses the TSV via unit 90 for testing a signal transmission state of each TSV in the TSV unit 90 in Paragraph [0040]) and SPRs (Fig. 1-6 Item 90a discloses the SPRs unit 90. When the test controller 120 receives a power-on signal (e.g., from an external source) for operating the semiconductor apparatus 10 in Paragraph [0027]).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify the voltage drop measured by a voltmeter and the resistance of the segment in Lund by substituting semiconductor chips are electrically connected through one or more through-silicon vias (TSVs) by WOO to control a test operation for testing the signal transmission state of each TSV in Paragraph [0047]).
Regarding to claim 8, Lund discloses the circuit of claim 1, wherein the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) measures a voltage across the via (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067) connected to the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) and the current source (Fig. 1-3 Item 10 or 22 discloses a conductor 10 capable of conducting electrical current in Col3 Lines 0019-0067) and
Lund does not explicitly teach is configured to output a signal that indicates whether the voltage is above or below a threshold voltage; and
the threshold voltage corresponds to a resistance level of a degraded via.
However, WOO teaches is configured to output a signal that indicates whether the voltage is above or below a threshold voltage; and
the threshold voltage corresponds to a resistance level of a degraded via (Fig. 1-6 Item 90a discloses the TSV unit 90 is abnormal due to various factors in a manufacturing process, a resistance value in Paragraph [0045]).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify the voltage drop measured by a voltmeter and the resistance of the segment in Lund by substituting semiconductor chips are electrically connected through one or more through-silicon vias (TSVs) by WOO to control a test operation for testing the signal transmission state of each TSV in Paragraph [0047]).
Regarding to claim 11, Lund discloses a method of testing a plurality of vias, comprising:
providing a circuit comprising a current source (Fig. 1-3 Item 10 or 22 discloses a conductor 10 capable of conducting electrical current in Col3 Lines 0019-0067) a plurality of switches ((Fig. 1-3 Item 20a & 20b] in Col3 Lines 0019-0067) and an analog-to-digital converter (ADC) (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) wherein the circuit is configured to connect to a device under testing and the device under testing comprises the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067);
connecting a first via of the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067) to the current source (Fig. 1-3 Item 10 or 22) using a first switch of the plurality of switches ((Fig. 1-3 Item 20a & 20b) through a first conductive path ((Fig. 1-3 Item 20c connect wire) and to a first wire using a second switch of the plurality of switches ((Fig. 1-3 Item 20a & 20b), wherein the first wire connects to a first input of the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067);
measuring the first via using the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067)
disconnecting (Fig. 1-3 Item 13) the first via of the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); from the current source (Fig. 1-3 Item 10 or 22 discloses a conductor 10 capable of conducting electrical current in Col3 Lines 0019-0067) and the first wire;
connecting a second via (Fig. 1-3 Item 12 & 16 discloses two-wire probe in
Col3 Lines 0019-0067) of the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067) to the current source (Fig. 1-3 Item 10 or 22) using a third switch of the plurality of switches (Fig. 1-3 Item 20a-20c) through the first conductive path ((Fig. 1-3 Item 20c wire) and to the first wire using a fourth switch of the plurality of switches (Fig. 1-3 Item 20a-20c); and
measuring the second via (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); using the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067)
Lund does not explicitly teach measuring a resistance of the first via
measuring a resistance of the second via.
However, WOO teaches measuring a resistance of the first via (Fig. 1-6 Item 90a discloses the TSV unit 90 is abnormal due to various factors in a manufacturing process, a resistance value in Paragraph [0045])
measuring a resistance of the second via (Fig. 1-6 Item 90a discloses the TSV unit 90 is abnormal due to various factors in a manufacturing process, a resistance value in Paragraph [0045])
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify the voltage drop measured by a voltmeter and the resistance of the segment in Lund by substituting semiconductor chips are electrically connected through one or more through-silicon vias (TSVs) by WOO to control a test operation for testing the signal transmission state of each TSV in Paragraph [0047]).
Lund does not explicitly teach a second conductive path that includes the first wire and that is electrically isolated from the first conductive path;
However, LI teaches a second conductive path that includes the first wire and that is electrically isolated from the first conductive path; (Fig. 1-2 discloses the conductive wire and to electrically isolate the conductive wire from the portion of the first conductive layer in Paragraph [0012])
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify the voltage drop measured by a voltmeter and the resistance of the segment in Lund by substituting a second conductive path that is electrically isolated from the first conductive path by LI to accurately measure electrically isolated first and second conductive wires in abstract.
Regarding to claim 12, Lund discloses the method of claim 11, wherein the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); comprises N number of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); of the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); and
Lund does not explicitly teach the method comprises measuring the resistance of N number of vias.
However, WOO teaches the method comprises measuring the resistance of N number of vias (Fig. 1-6 Item 90a discloses the TSV unit 90 is abnormal due to various factors in a manufacturing process, a resistance value in Paragraph [0045])
measuring a resistance of the second via (Fig. 1-6 Item 90a discloses the TSV unit 90 is abnormal due to various factors in a manufacturing process, a resistance value in Paragraph [0045])
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify the voltage drop measured by a voltmeter and the resistance of the segment in Lund by substituting semiconductor chips are electrically connected through one or more through-silicon vias (TSVs) by WOO to control a test operation for testing the signal transmission state of each TSV in Paragraph [0047]).
Regarding to claim 13, Lund discloses the method of claim 11, wherein the connecting the first via (Fig. 1-3 Item 12), disconnecting (Fig. 1-3 Item 20) the first via (Fig. 1-3 Item 12), connecting (Fig. 1-3 Item 20) the second via (Fig. 1-3 Item 16), and disconnecting (Fig. 1-3 Item 20) the second via (Fig. 1-3 Item 16), is controlled by a digital controller (Fig. 1-3 Item 30).
Regarding to claim 14, Lund discloses the method of claim 11, wherein the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); are configured to connect to a second input of the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) through a plurality of second wires having a one-to-one correspondence with the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067);
Regarding to claim 15, Lund discloses the method of claim 11, wherein each of the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); are connected (Fig. 1-3 Item 20) to a second wire that is configured to connect the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); to a second input of the ADC (Fig. 1-3 Item 28).
Regarding to claim 16, Lund discloses the method of claim 11, wherein the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) comprises
Lund does not explicitly teach a second input that is connected to a reference voltage; and the measuring a resistance of the first via and measuring a resistance of the second via comprises comparing a voltage measured at the first input to the reference voltage.
However, WOO teaches a second input that is connected to a reference voltage; and the measuring a resistance of the first via and measuring a resistance of the second via comprises comparing a voltage measured at the first input to the reference voltage (Fig. 1-6 Item 90a discloses the TSV unit 90 is abnormal due to various factors in a manufacturing process, a resistance value in Paragraph [0045])
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify a measuring current in an electric power distribution system in Lund by substituting semiconductor chips are electrically connected through one or more through-silicon vias (TSVs) by WOO to control a test operation for testing the signal transmission state of each TSV in Paragraph [0047]).
Regarding to claim 17, Lund discloses a testing system, comprising:
a plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); disposed within the substrate and extending between the first surface and the second surface;
an analog-to-digital converter (ADC) (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) disposed in the device and routing layer and having a first input connected to a first wire, wherein the first wire is configured to be connected to the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); by a plurality of switches ((Fig. 1-3 Item 20a & 20b] in Col3 Lines 0019-0067) and
wherein the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) is configured to output a signal that represents resistance values of the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067);
wherein the circuit further comprises a current source (Fig. 1-3 Item 10 or 22 discloses a conductor 10 capable of conducting electrical current in Col3 Lines 0019-0067) configured to deliver a constant current supply to the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067);
wherein the current source (Fig. 1-3 Item 10 or 22) is connected to a selected via of the plurality of vias (Fig. 1-3 Item 12 & 16) through a first conductive path (Fig. 1-3 Item 230 c wire);
wherein the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067) is connected to the selected via (Fig. 1-3 Item 12 & 16) through a second conductive path (Fig. 1-3 Item 230 b wire). that includes the first wire (Fig. 1-3 Item 230 c wire).
Lund does not explicitly teach a device under testing; and
a circuit;
the device under testing comprising:
a substrate comprising a first surface and a second surface opposite the first surface;
a device and routing layer disposed over the substrate; and
a backside routing layer disposed below the substrate;
the circuit comprising:
at least one second wire disposed in the backside routing layer and connected to at least one via of the plurality of vias on a bottom side of the at least one via,
However, WOO teaches a circuit;
the device under testing (Fig. 1-6 Item 90 & 100) comprising:
a substrate (Fig. 1-6 Item 90 discloses the TSV unit 90 is abnormal due to various factors in a manufacturing process, a resistance value in Paragraph [0045])
comprising a first surface (Fig. 1-6 Item 90 top) and a second surface (Fig. 1-6 Item 90 bottom) opposite the first surface;
a device and routing layer (Fig. 1-6 Item 100+1A) disposed over the substrate (Fig. 1-6 Item 90); and
a backside routing layer (Fig. 1-6 Item 100+2A) disposed below the substrate (Fig. 1-6 Item 90);
the circuit comprising:
at least one second wire (Fig. 1-6 Item 90 - tsv2) disposed in the backside routing layer (Fig. 1-6 Item 100+2A) and connected to at least one via (Fig. 1-6 Item 90 -TSV1) of the plurality of vias on (Fig. 1-6 Item 90 -TSV1 & tsv2) a bottom side of the at least one via,
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify the voltage drop measured by a voltmeter and the resistance of the segment in Lund by substituting semiconductor chips are electrically connected through one or more through-silicon vias (TSVs) by WOO to control a test operation for testing the signal transmission state of each TSV in Paragraph [0047]).
Lund does not explicitly teach the first wire and the at least one second wire and is electrically isolated from the first conductive path;
However, LI teaches the first wire and the at least one second wire and is electrically isolated from the first conductive path; (Fig. 1-2 discloses the conductive wire and to electrically isolate the conductive wire from the portion of the first conductive layer in Paragraph [0012])
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify the voltage drop measured by a voltmeter and the resistance of the segment in Lund by substituting a second conductive path that is electrically isolated from the first conductive path by LI to accurately measure electrically isolated first and second conductive wires in abstract.
Regarding to claim 18, Lund discloses the system of claim 17.
Lund does not explicitly teach wherein the circuit further comprises a current source disposed in the device and routing layer and configured to supply a constant current.
However, WOO teaches wherein the circuit (Fig. 1-6 Item 100) further comprises a current source disposed in the device and routing layer (Fig. 1-6 Item 100+2A) and configured to supply a constant current (Fig. 1-6 Item A1 or A2).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify the voltage drop measured by a voltmeter and the resistance of the segment in Lund by substituting semiconductor chips are electrically connected through one or more through-silicon vias (TSVs) by WOO to control a test operation for testing the signal transmission state of each TSV in Paragraph [0047]).
Regarding to claim 19, Lund discloses the system claim 17, wherein the at least one second wire comprises a plurality of second wires having a one-to-one correspondence with the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067).
Regarding to claim 20, Lund discloses the system claim 17, wherein the at least one second wire is connected to each of the plurality of vias (Fig. 1-3 Item 12 & 16 discloses two-wire probe in Col3 Lines 0019-0067); and is further connected to a second input of the ADC (Fig. 1-3 Item 28 voltmeter includes an “ADC” in Col3 Lines 0019-0067).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENT J ANDREWS whose telephone number is (571)272-6101. The examiner can normally be reached 10am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at (571)272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRENT J ANDREWS/Examiner, Art Unit 2858
/JUDY NGUYEN/Supervisory Patent Examiner, Art Unit 2858
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