DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/21/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 5-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ide et al. (US 20200096558 A1).
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Regarding claim 1, Ide discloses a circuit for detecting via degradation, comprising:
a current source (Fig. 1 & 5 Item 538 discloses a current supply circuit 538 in Paragraph [0045]) configured to deliver a constant current supply (Fig. 1 & 5 Item 538 discloses a current supply circuit 538 to generate a constant reference current in Paragraph [0045]) to a plurality of conductive vias (Fig. 1 & 5 Item 110 or 510 discloses a plurality TSVs vias 110 in Paragraph [0003-0004]) of a device under testing (Fig. 1 & 5);
a plurality of switches (Fig. 1 & 5 Item 540 a & 540 b discloses 540 a and 540 b include transistors which may act as switches in Paragraph [0042]) configured to connect the current source (Fig. 1 & 5 Item 538) to the plurality of vias (Fig. 1 & 5 Item 110 or 510; and
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an analog-to-digital converter (ADC) (Applicant discloses ADC is comparator in paragraph [0042] Fig. 1 & 5 Item 106 or 532 discloses the comparator 106 connected to TSV 110 in Paragraph [0004]) configured to be connected to the plurality of vias (Fig. 1 & 5 Item 106 discloses the comparator 106 connected to TSV 110 in Paragraph [0004]) by the plurality of switches (Fig. 1 & 5 Item 540 a & 540 b) through a first wire, wherein the first wire is connected to a first input of the ADC(Fig. 1 & 5 Item 106 connected to comparator),
wherein the plurality of switches (Fig. 1 & 5 Item 540 a & 540 b) are configured to connect one via of the plurality of vias (Fig. 1 & 5 Item 110 or 510) at a time to the current source (Fig. 1 & 5 Item 538) and to the first wire; and
wherein the ADC (Fig. 1 & 5 Item 106) is configured to output a signal that represents the resistance (Fig. 1 & 5 Item 536 discloses resistance tested as well as other TSVs 510 and a signal TSV 536 in Paragraph [0042]) by the plurality of switches (Fig. 1 & 5 Item 540 a & 540 b) of a via (Fig. 1 & 5 Item 110 or 510) the plurality of vias connected to the ADC (Fig. 1 & 5 Item 106) and the current sources (Fig. 1 & 5 Item 538)
Regarding claim 2, Ide discloses the circuit of claim l, wherein the plurality of vias comprises a plurality of through-silicon-vias (T S Vs) (Fig. 1 & 5 Item 110 or 510 discloses a plurality TSVs vias 110 in Paragraph [0003-0004]).
Regarding claim 5, Ide discloses the circuit of claim l, further comprising a plurality of second wires (Fig. 1 & 5 Item 110 or 510 output wires) connected to the plurality of vias (Fig. 1 & 5 Item 110 or 510) in a one-to-one correspondence; and
a plurality of return vias in a one-to-one correspondence with the plurality of second wires (Fig. 1 & 5 Item 110 or 510 output wires) and the plurality of vias (Fig. 1 & 5 Item 110 or 510).
Regarding claim 6, Ide discloses the circuit of claim l, further comprising a second wire (Fig. 1 & 5 Item 110 or 510 output wires) connected to each of the plurality of vias (Fig. 1 & 5 Item 110 or 510), wherein the second wire is configured to connect the plurality of vias (Fig. 1 & 5 Item 110 or 510) to a second input of the ADC (Fig. 1 & 5 Item 106 second input).
Regarding claim 7, Ide discloses the circuit of claim l, wherein the ADC comprises a second input (Fig. 1 & 5 Item 106 second input) that is connected to a reference voltage (Fig. 1 & 5 Item 106 coupled to ground).
Regarding claim 8, Ide discloses the circuit of claim l, wherein the ADC (Fig. 1 & 5 Item 106 or 532) measures a voltage across the via connected to the ADC (Fig. 1 & 5 Item 106 or 532) and the current source (Fig. 1 & 5 Item 538), and is configured to output a signal that indicates whether the voltage is above or below a threshold voltage (Fig. 1 & 5 discloses TSVs may be tested for a pass/rejection in Paragraph [0066]); and
the threshold voltage corresponds to a resistance level of a degraded via (Fig. 1 & 5 item 538 discloses TSV resistance test is activated (e.g., by application of an appropriate voltage to couple the target TSV 510′ in Paragraph [0043]).
Regarding claim 9, Ide discloses the circuit of claim l, further comprising a digital controller (Fig. 1 & 5 Item 540a or 540 b coupled to controller [0063]), wherein the digital controller is configured to control the plurality of switches (Fig. 1 & 5 Item 540a or 540 b) to connect the plurality of vias (Fig. 1 & 5 Item 110 or 510) to the current source (Fig. 1 & 5 Item 538) and the ADC in a pre-determined order (Fig. 1 & 5 Item 106 or 532).
Regarding claim 10, Ide discloses the circuit of claim l, wherein the ADC comprises a comparator (Fig. 1 & 5 Item 106 or 532 discloses the comparator 106 connected to TSV 110 in Paragraph [0004]).
Regarding claim 11, Ide discloses a method of testing a plurality of vias, comprising:
providing a circuit comprising a current source (Fig. 1 & 5 Item 538 discloses a current supply circuit 538 in Paragraph [0045]), a plurality of switches, and an analog-to-digital converter (ADC) (Applicant discloses ADC is comparator in paragraph [0042] Fig. 1 & 5 Item 106 or 532 discloses the comparator 106 connected to TSV 110 in Paragraph [0004]),
wherein the circuit is configured to connect to a device under testing (Fig. 1 & 5 Item 100 or 500) and the device under testing comprises the plurality of vias (Fig. 1 & 5 Item 110 or 510 discloses a plurality TSVs vias 110 in Paragraph [0003-0004]).
connecting (Fig. 1 & 5 Item 540 a discloses 540 a and 540 b ate connect switches in Paragraph [0042]) a first via the plurality of vias (Fig. 1 & 5 Item 110 or 510 discloses a plurality TSVs vias 110 in Paragraph [0003-0004]) to the current source (Fig. 1 & 5 Item 538) using a first switch (Fig. 1 & 5 Item 540 a ) of the plurality of switches (Fig. 1 & 5 Item 540 a & 540 b discloses 540 a and 540 b include transistors which may act as switches in Paragraph [0042]) and to a first wire using a second switch (Fig. 1 & 5 Item 540 b ) of the plurality of switches ((Fig. 1 & 5 Item 540 a & 540 b ),
wherein the first wire connects to a first input of the ADC (Fig. 1 & 5 Item
106 or 532 top input) measuring a resistance of the first via of the plurality of vias (Fig. 1 & 5 Item 110 or 510) using the ADC (Fig. 1 & 5 Item 106).
disconnecting (Fig. 1 & 5 Item 540 or 114 select switches disconnect) the first via of the plurality of vias (Fig. 1 & 5 Item 110 or 510) from the current source (Fig. 1 & 5 Item 538) and the first wire; connecting a second via (Fig. 1 & 5 Item 110 or 519) of the plurality of vias (Fig. 1 & 5 Item 110 or 510) to the current source (Fig. 1 & 5 Item 538) using a third switch (Fig. 1 & 5 Item 540 which have four switches in Paragraph [0042]) of the plurality of switches (Fig. 1 & 5 Item 540 or 114) and to the first wire using a fourth switch (Fig. 1 & 5 Item 540 which have four switches in Paragraph [0042]) of the plurality of switches; and
measuring a resistance (Fig. 1 & 5 Item 536 & 532 discloses resistance tested as well as other TSVs 510 and a signal TSV 536 in Paragraph [0042]) of the second via using the ADC (Fig. 1 & 5 Item 106 or 532)
Regarding claim 12, Ide discloses the method of claim I l, wherein the plurality of vias comprises N number of vias (Fig. 1 & 5 Item 110 or 510); and the method comprises measuring the resistance of N number of vias (Fig. 1 & 5 Item 536 & 532 discloses resistance tested as well as other TSVs 510 and a signal TSV 536 in Paragraph [0042]).
Regarding claim 13, Ide discloses the method of claim I l, wherein the connecting the first via (Fig. 1 & 5 Item 510), disconnecting the first via (Fig. 1 & 5 Item 540 can disconnect), connecting the second via (Fig. 1 & 5 Item 510-2), and disconnecting the second via (Fig. 1 & 5 Item 510-2), is controlled by a digital controller (Fig. 1 & 5 Item 540a or 540 b coupled to controller [0063]).
Regarding claim 14, Ide discloses the method of claim I l, wherein the
plurality of vias (Fig. 1 & 5 Item 110 or 510) are configured to connect to a
Second input of the ADC (Fig. 1 & 5 Item 106 or 532 top input) through a plurality of second wires having a one-to-one correspondence with the plurality of vias (Fig. 1 & 5 Item 110 or 510).
Regarding claim 15, Ide discloses the method of claim I l, wherein each of
the plurality of vias (Fig. 1 & 5 Item 110 or 510) are connected to a second wire that is configured to connect the plurality of vias (Fig. 1 & 5 Item 110 or 510) to a second input of the ADC (Fig. 1 & 5 Item 106 or 532 top input).
Regarding claim 16, Ide discloses the method of claim I l, wherein the ADC
comprises a second input (Fig. 1 & 5 Item 106 or 532 bottom input) that is connected to a reference voltage (Fig. 1 & 5 Item 106 coupled to ground); and the measuring a resistance of the first via (Fig. 1 & 5 Item 110 or 510) and measuring a resistance of the second via (Fig. 1 & 5 Item 110 or 510) comprises comparing (Fig. 1 & 5 Item 106 or 532) a voltage measured at the first input to the reference voltage (Fig. 1 & 5 Item 106 coupled to ground).
Regarding claim 17, discloses a testing system, comprising:
a device under testing (Fig. 1 & 5 Item 100 or 500); and
a circuit; the device under testing (Fig. 1 & 5 Item 100 or 500) comprising:
a substrate (Fig. 1 & 5 Item 102) comprising a first surface and a second surface opposite the first surface; a plurality of vias (Fig. 1 & 5 Item 110 or 510 discloses a plurality TSVs vias 110 in Paragraph [0003-0004]) disposed within the substrate (Fig. 1 & 5 Item 102) and extending between the first surface and the second surface; a device and routing layer disposed over the substrate (Fig. 1 & 5 Item 102); and a backside routing layer (Fig. 1 & 5 Item 104) disposed below the substrate (Fig. 1 & 5 Item 102); the circuit comprising:
a plurality of switches (Fig. 1 & 5 Item 540 a & 540 b discloses 540 a and 540 b include transistors which may act as switches in Paragraph [0042]) disposed in the device (Fig. 1 & 5 Item 100 or 500) and routing layer (Fig. 1 & 5 Item 104) and coupled to the plurality of vias (Fig. 1 & 5 Item 110 or 510), the plurality of switches (Fig. 1 & 5 Item 540 a & 540 b) configured to couple a selected via of the plurality of vias (Fig. 1 & 5 Item 110 or 510) to receive a testing current, an analog-to-digital converter (ADC) (Applicant discloses ADC is comparator in paragraph [0042] Fig. 1 & 5 Item 106 or 532 discloses the comparator 106 connected to TSV 110 in Paragraph [0004]) disposed in the device and routing layer (Fig. 1 & 5 Item 104) and having a first input connected to a first wire (Fig. 1 & 5 Item 106 or 532 input wire) ,
wherein the first wire is configured to be connected to the selected via of the plurality of vias (Fig. 1 & 5 Item 110 or 510) by the plurality of switches (Fig. 1 & 5 Item 540 a & 540 b).
at least one second wire (Fig. 1 & 5 Item 106 or 532 second input wire) disposed in the backside routing layer (Fig. 1 & 5 Item 104) and connected to at least one via the selected via of the plurality of vias (Fig. 1 & 5 Item 110 or 510 discloses a plurality TSVs vias 110 in Paragraph [0003-0004]) on a bottom side of at least one selected via (Fig. 1 & 5 Item 110 or 510).
Regarding claim 18, discloses the system of claim 17, wherein the circuit
further comprises a current source (Fig. 1 & 5 Item 538) disposed in the device and routing layer (Fig. 1 & 5 Item 104) and configured to supply a constant current (Fig. 1 & 5 Item 538 discloses a current supply circuit 538 to generate a constant reference current in Paragraph [0045]).
Regarding claim 19, discloses the system claim 17, wherein the at least
one second wire comprises a plurality of second wires (Fig. 1 & 5 Item 110 or 510 output wire) having a one-to-one correspondence with the plurality of vias (Fig. 1 & 5 Item 110 or 510 discloses a plurality TSVs vias 110 in Paragraph [0003-0004]).
Regarding claim 20, discloses the system claim 17, wherein the at least
one second wire is connected to each of the plurality of vias (Fig. 1 & 5 Item 110 or 510 discloses a plurality TSVs vias 110 in Paragraph [0003-0004]).and is further connected to a second input of the ADC (Fig. 1 & 5 Item 106 or 532 discloses second input in Paragraph [0004]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3-4 are rejected under 35 U.S.C. 103(a) as being unpatentable over Ide et al. (US 20200096558 A1) in view of WOO et al. (US 20170059648 A1).
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Regarding claim 3, Ide discloses the circuit of claim 1.
Ide does not explicitly teach wherein the plurality of vias comprises a plurality of super power rails (SPRs).
However, WOO teaches wherein the plurality of vias comprises a plurality of super power rails (SPRs) (Fig. 1-6 Item 90a discloses the SPRs unit 90. When the test controller 120 receives a power-on signal (e.g., from an external source) for operating the semiconductor apparatus 10 in Paragraph [0027])
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify an apparatuses and methods for testing through silicon vias (TSVs) in Ide by substituting semiconductor chips are electrically connected through one or more super power rails (SPRs) by WOO to control a test operation for testing the signal transmission state of each TSV in Paragraph [0047]).
Regarding claim 4, Ide discloses the circuit of claim 1,
Ide does not explicitly teach wherein the plurality of vias comprises both TSVs and SPRs.
However, WOO teaches wherein the plurality of vias comprises both TSVs (Fig. 1-6 Item 90a discloses the TSV via unit 90 for testing a signal transmission state of each TSV in the TSV unit 90 in Paragraph [0040]) and SPRs (Fig. 1-6 Item 90a discloses the SPRs unit 90. When the test controller 120 receives a power-on signal (e.g., from an external source) for operating the semiconductor apparatus 10 in Paragraph [0027]).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claimed invention, to modify an apparatuses and methods for testing through silicon vias (TSVs) in Ide by substituting semiconductor chips are electrically connected through one or more super power rails (SPRs) by WOO to control a test operation for testing the signal transmission state of each TSV in Paragraph [0047]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENT J ANDREWS whose telephone number is (571)272-6101. The examiner can normally be reached 10am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at (571)272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRENT J ANDREWS/Examiner, Art Unit 2858
/STEVEN L YENINAS/Primary Examiner, Art Unit 2858
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