DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Priority
2. Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 02/16/2024 is being considered by the Examiner.
Disposition of the Claims
4. The instant application was effectively filed on December 1, 2022, wherein claims 1-12 are pending.
Examiner NOTEs: in order to expedite prosecution, Examiner initiated a call with Applicants Attorney on 12/31/2025 suggesting that independent claim 1 and its dependents as recited are found allowable however, independent claim 8 can still be rejected using prior art reference Miyake-(20200194474 A1; see Fig.’s 43a and 43b) but would be allowable if claim 9 is rolled into claim 8. Upon review, Applicant responded 1/5/2026 stating they would like to move forward and proceed with rejection. Therefore, non-final rejection appears to the record.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyake US PG-PUB 20200194471 A1 (hereinafter Miyake).
Regarding claim 8, Miyake teaches A semiconductor device comprising: a first transistor (Fig. 43a; Tr1); a second transistor (Fig. 43a; DrTr); a third transistor (Fig. 43a; Tr2); a fourth transistor (Fig. 43a; Tr3); and a light-emitting element (Fig. 43a; OLED), wherein a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor (Fig. 43a; gate of DrTr is connected to of Tr1), wherein the second transistor comprises a back gate (Fig. 43a; DrTr has a back gate), wherein the back gate of the second transistor is electrically connected to one of a source and a drain of the fourth transistor (Fig. 43; back gate of DrTr is connected to Tr3), wherein the second transistor is configured to control the amount of current flowing through the light-emitting element in accordance with a potential supplied to the gate of the second transistor and to change a threshold voltage of the second transistor in accordance with a potential supplied to the back gate of the second transistor (Fig. 43a and Para. [0408]; Note that in Period I, G3 is high and Tr4 is on, and the source potential of the driving transistor DrTr is the sum of a CATHODE potential and a threshold of the OLED (V.sub.thOLED). and Para. [0415]; when the threshold voltage V.sub.th of the driving transistor DrTr is positive, the V.sub.th can be compensated in a range of V.sub.th from 0 to a value positively shifted by a potential of V.sub.0−(Cathode+V.sub.thOLED), note that V.sub.thOLED denotes a threshold of the OLED, and when the threshold voltage of the driving transistor DrTr is negative, the V.sub.th can be compensated in a range from 0 to a value negatively shifted by a potential of Anode−V.sub.0. When variation in the threshold voltage of the driving transistor DrTr is within the range of positive, the power source of a power supply line V.sub.0 can be referred to as Anode, in which case one power supply line V.sub.0 in the pixel can be removed), and wherein a frequency of turning on the fourth transistor is lower than a frequency of turning on the first transistor (Fig. 43a and 43b; as depicted in Fig. 43b, the “on” period of G2 is larger than the “on” period of G1. Thus, since frequency is inversely proportional to period, the frequency of G2 will be lower than the frequency of G1).
Allowable Subject Matter
Claims 1-7 are allowed.
Regarding claim 1, closet prior art Miyake teaches pixel circuit struct as disclosed in Fig. 43a. However, none of the references cited either alone or in any obvious combination teaches and/or suggest “wherein the first transistor comprises a first semiconductor layer, wherein part of the first semiconductor layer is in a first opening in the insulating layer, wherein the third transistor comprises a second semiconductor layer, wherein part of the second semiconductor layer is in a second opening in the insulating layer, wherein the fourth transistor comprises a third semiconductor layer, and wherein part of the third semiconductor layer is in a third opening in the insulating layer”
Claims 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, none of the references cited either alone or in any obvious combination teaches and/or suggest “wherein part of the first semiconductor layer is in a first opening in the insulating layer, wherein the fourth transistor comprises a third semiconductor layer, and wherein part of the third semiconductor layer is in a third opening in the insulating layer”.
Conclusion
5. The following Prior Arts made of record that were not relied upon for rejection purpose in this office Action were in combination considered to be pertinent to the applicant's disclosure such that one of ordinary skill in the art would modify them to arrive at the claimed invention.
Okazaki et al. (US PG-PUB 20220320184 A1) teaches Para. [0486] An opening reaching the semiconductor layer 321 is provided in the insulating layers 328 and 264. The insulating layer 323 that is in contact with side surfaces of the insulating layers 264 and 328, a side surface of the conductive layer 325, and the top surface of the semiconductor layer 321 and the conductive layer 324 are embedded in the opening. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer. Para. [0556]; the semiconductor layer 451 in openings provided in the insulating layer 426 . And Para. [0538] The transistor 410 includes a semiconductor layer 411, an insulating layer 412, a conductive layer 413, and the like. The semiconductor layer 411 includes a channel formation region 411i and low-resistance regions 411n. The semiconductor layer 411 contains silicon. The semiconductor layer 411 preferably contains polycrystalline silicon. Part of the insulating layer 412 functions as a gate insulating layer. The conductive layer 413 functions as a gate electrode.
Miyake et al. (US Patent# 9,230,996 B2) teaches a light-emitting device includes at least a first wiring, a second wiring, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a capacitor, and a light-emitting element. The first transistor has a function of controlling conduction between the first wiring and a first electrode of the capacitor. A second electrode of the capacitor is electrically connected to one of a source electrode and a drain electrode of the fifth transistor. The second transistor has a function of controlling conduction between the second wiring and a gate electrode of the fifth transistor. The third transistor has a function of controlling conduction between the first electrode of the capacitor and the gate electrode of the fifth transistor. The fourth transistor has a function of controlling conduction between the one of the source electrode and the drain electrode of the fifth transistor and an anode of the light-emitting element. A semiconductor film of each of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor includes a first semiconductor region overlapping with a gate electrode, a second semiconductor region in contact with a source electrode or a drain electrode, and a third semiconductor region between the first semiconductor region and the second semiconductor region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY ONYEKABA whose telephone number is (571)270-7633. The examiner can normally be reached on 9-5.
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/AMY ONYEKABA/Primary Examiner, Art Unit 2628