DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species A and Species I in the reply filed on 22 May 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 18-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species (B and II), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 22 May 2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 22 November 2023 and 8 August 2024 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshitaka Nakamura et al. (US 2022/0059693 A1; hereinafter “Nakamura”).
Regarding Claim 12, Nakamura teaches a semiconductor memory device comprising:
a substrate (56, Fig. 9A, para [0049] describes a substrate 56);
a conductive line on the substrate and extending in a first direction (16, 58 and 66, Fig. 9A, para [0017] describes a conductive structure 16 comprising a conductive material 58 and a second conductive material 66 wherein para [0028] describes first linear structures 16 extends in a y-axis direction);
an interfacial conductive pattern extending in the first direction on the conductive line (ICP and 28, annotated Fig. 9A and Fig. 9B, para [0021] and para [0028] describes a conductive oxide material 28 and ICP extending in the first Y-axis direction on the conductive line 58 and 66); and
a channel structure on the interfacial conductive pattern and comprising an oxide semiconductor material (26 and 30, annotated Fig. 9A, para [0022] describes a semiconductor material corresponding to a channel region 30 wherein para [0025] describes the channel structure 26 and 30 may comprise an oxide semiconductor material and further wherein the channel structure 26 and 30 are on the interfacial conductive pattern ICP),
wherein a contact area between the interfacial conductive pattern and the channel structure (ICP, 26 and 30, annotated Fig. 9A depicts a contact area between the interfacial conductive pattern ICP and the channel structure 26 and 30 that extends an entire length of the interfacial conductive pattern ICP on an upper side) is greater than a contact area between the interfacial conductive pattern and the conductive line (ICP, 58 and 66, annotated Fig. 9A, para [0063] describes first conductive material 58 and second conductive material 66 forming the lower conductive line wherein the contact area between the interfacial conductive pattern ICP and the lower conductive line 66 and 58 is less than that of the contact area between the interfacial conductive material ICP and the channel structure 26 and 30 as shown in Fig. 9A).
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Regarding Claim 13, Nakamura teaches the semiconductor memory device of claim 12, wherein the interfacial conductive pattern covers an entire upper surface of the conductive line (ICP and 66, annotated Fig. 9A depicts wherein the interfacial conductive pattern ICP covers an entire upper surface 66 of the conductive line 58 and 66 in at least an x-axis direction).
Regarding Claim 14, Nakamura teaches the semiconductor memory device of claim 12, wherein the channel structure (26 and 30, Fig. 9A) comprises:
a horizontal channel portion that is in direct contact with the interfacial conductive pattern (HCP and ICP, annotated Fig. 9A and annotated Fig. 9A II depicts a horizontal channel portion CHP in direct contact with the interfacial conductive pattern ICP) and extends along an upper surface of the interfacial conductive pattern in a second direction that intersects with the first direction (HCP and ICP, annotated Fig. 9A and annotated Fig. 9A II depicts wherein the horizontal channel portion HCP extends along an upper surface of the interfacial conductive pattern ICP in a second X-axis direction that intersects with the first Y-axis direction); and
a vertical channel portion extending in a vertical direction on the horizontal channel portion (VCP and HCP, annotated Fig. 9A II depicts a vertical channel portion VCP that extends in a vertical Z direction on the horizontal channel portion HCP), and
wherein a width of the horizontal channel portion in the second direction is equal to a width of the interfacial conductive pattern in the second direction (ICP and HCP, annotated Fig. 9A and annotated Fig. 9A II depicts wherein the interfacial conductive pattern ICP and horizontal channel portion HCP are disposed along sidewalls of an insulative material 36 as described in para [0027] resulting in the horizontal channel portion HCP and interfacial conductive pattern ICP having an equal width in the second X-direction).
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Regarding Claim 15, Nakamura teaches the semiconductor memory device of claim 14, wherein a side surface of the interfacial conductive pattern and a side surface of the channel structure are vertically aligned with each other (ICP, 26 and 30, annotated Fig. 9A, para [0027] describes wherein a side surface of the channel portion 26 and 30 and a side surface of the interfacial conductive pattern ICP are enclosed by the insulative material 36 as shown in annotated Fig. 9A resulting in a side surface of the channel portion 26 and 30 and a side surface of the interfacial conductive pattern ICP being vertically aligned with each other).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshitaka Nakamura et al. (US 2022/0059693 A1; hereinafter “Nakamura”) in view of Min Chul Sung (US 2023/0164977 A1; hereinafter “Sung”).
Regarding Claim 16, Nakamura discloses all the limitations of claim 12.
Nakamura fails to explicitly disclose the semiconductor memory device of claim 12, wherein the interfacial conductive pattern and the conductive line comprise a same metal.
However, Sung teaches a similar semiconductor memory device, wherein the interfacial conductive pattern (111, Fig. 1D, para [0040] describes a barrier layer 111 at an interface between the channel structure 121 and a lower conductive line 110) and the lower conductive line include a same metal (111, Fig. 1D, para [0040] describes wherein the interfacial conductive pattern 111 may comprise a material such as molybdenum and Nakamura teaches in para [0017] wherein the lower conductive line 58 and 66 may comprise a conductive material 58 such as molybdenum therefore the interfacial conductive pattern 111 of Sung and the lower conductive line 58 and 66 of Nakamura may comprise a same molybdenum metal material).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Nakamura with Sung to further disclose a semiconductor memory device wherein the interfacial conductive pattern and the lower conductive line include a same material in order to provide the well-known advantage of simplifying a manufacturing process by requiring a same metal material for subsequent device layers lowering manufacturing time and therefore reducing manufacturing costs.
Claims 1-9, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshitaka Nakamura et al. (US 2022/0059693 A1; hereinafter “Nakamura”) in view of Min Chul Sung (US 2023/0164977 A1; hereinafter “Sung”) and in further view of Tomoaki Sawabe et al. US 2019/0296155 A1; hereinafter “Sawabe”).
Regarding Claim 1, Nakamura teaches a semiconductor memory device comprising:
a substrate (56, Fig. 9A, para [0049] describes a substrate 56);
a lower conductive line on the substrate (16, 58 and 66, Fig. 9A, para [0017] describes a conductive structure 16 comprising a conductive material 58 and a second conductive material 66);
an isolation insulating layer on the lower conductive line and comprising a channel trench (39, Fig. 9A, para [0030] describes an insulative material 39 over the conductive structures and comprising a trench wherein channels are formed);
a channel structure inside the channel trench and comprising a first oxide semiconductor material (26 and 30, Fig. 9A, para [0022] describes a semiconductor material corresponding to a channel region 30 wherein para [0025] describes the channel structure 26 may comprise an oxide semiconductor material);
an interfacial conductive pattern between the lower conductive line and a lower surface of the channel structure (ICP and 28, annotated Fig. 9A, para [0021] describes a conductive oxide material 28 and ICP between the lower conductive line 58 and 66 and a lower surface of the channel structure 26 and 30);
a gate dielectric layer that covers the channel structure within the channel trench (36, Fig. 9A, para [0027] describes a gate dielectric material 36 covering the channel structure 26 and 30);
an upper conductive line on the gate dielectric layer within the channel trench (40, Fig. 9B, para [0028] describes a conductive gate material 40 on the gate dielectric layer 36);
a conductive contact pattern on the channel structure (74, Fig. 9A, para [0063] describes a conductive material 74 formed on the channel structure 26 and 30); and
a capacitor structure (14, Fig. 2A, para [0065] describes wherein storage elements, which may be capacitors as described in para [0016], are coupled to interconnects 50) comprising a lower electrode connected to the conductive contact pattern (50, Fig. 9A, para [0065] describes an interconnect structure 50 for a capacitor 14 connected to the conductive contact pattern 74),
wherein a contact area between the interfacial conductive pattern and the channel structure (ICP, 26 and 30, annotated Fig. 9A depicts a contact area between the interfacial conductive pattern ICP and the channel structure 26 and 30 that extends an entire length of the interfacial conductive pattern ICP on an upper side) is greater than a contact area between the interfacial conductive pattern and the lower conductive line (ICP, 58 and 66, annotated Fig. 9A, para [0063] describes first conductive material 58 and second conductive material 66 forming the lower conductive line wherein the contact area between the interfacial conductive pattern ICP and the lower conductive line 66 and 58 is less than that of the contact area between the interfacial conductive material ICP and the channel structure 26 and 30 as shown in Fig. 9A).
Nakamura fails to explicitly disclose an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and comprising a second oxide semiconductor material.
However, Sung teaches a similar semiconductor memory device comprising an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern (123, 126 and 121 Fig. 1D, para [0031] describes an upper interface layer 123 comprised between a channel structure 121 and a conductive contact pattern 126 wherein the interfacial oxide semiconductor pattern 123 may comprise an oxide semiconductor interface layer) and comprising a second oxide semiconductor material (123, Fig. 1D, para [0041] describes wherein the interfacial oxide semiconductor pattern 123 may comprise a second oxide semiconductor pattern such as indium-rich IGZO).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Nakamura with Sung to further disclose a semiconductor memory device comprising an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and comprising a second oxide semiconductor material in order to provide the advantage of providing an interface material layer which may have a lower resistance than the channel layer in order to provide an ohmic contact between a channel and conductive contact and to enable a seamless interconnection of a channel material to a memory structure (Sung, para [0060]).
Nakamura and Sung fail to explicitly disclose wherein a contact area between the interfacial oxide semiconductor pattern and the conductive contact pattern is greater than a contact area between the interfacial oxide semiconductor pattern and the channel structure.
However, Sawabe teaches a similar semiconductor memory device, wherein a contact area between the interfacial oxide semiconductor pattern (62, Fig. 12, para [0095] describes an auxiliary layer 62 which may comprise a same oxide semiconductor material as the interfacial oxide semiconductor pattern of Sung, such as gallium oxide containing indium and zinc) and the conductive contact pattern (14, Fig. 12, para [0095] describes a drain electrode 14 comprising a conductive contact) is greater than a contact area between the interfacial oxide semiconductor pattern and the channel structure (62, 14 and 16, Fig. 12, para [0095] describes a channel layer structure 16 wherein a contact area between the interfacial oxide semiconductor pattern 62 and the conductive contact pattern 14 extends along an entire upper surface of the interfacial oxide semiconductor pattern 62 and wherein a contact area between the interfacial oxide semiconductor pattern 62 and channel structure 16 extends along a portion of a lower surface of the interfacial oxide semiconductor pattern 62).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Nakamura and Sung with Sawabe to further disclose a semiconductor memory device wherein a contact area between an interfacial oxide semiconductor pattern and a conductive contact pattern is greater than a contact area between the interfacial oxide semiconductor pattern and a channel structure in order to provide the advantage of providing an interfacial oxide semiconductor pattern which can reduce a resistance between an electrode and a channel layer so that an on-resistance of a device may be reduced therefore lowering operating costs.
Regarding Claim 2, the combination of Nakamura, Sung and Sawabe discloses the semiconductor memory device of claim 1,
wherein the upper conductive line extends in a first direction (Nakamura, 40, Fig. 9A and Fig. 9B, para [0028] describes wherein the upper conductive line 40 extends along a first X-axis direction),
wherein each of the lower conductive line and the interfacial conductive pattern extends in a second direction that intersects with the first direction (Nakamura, 16, 58, 66 and ICP, annotated Fig. 9A and Fig. 9B, para [0028] describes wherein the first linear structures 16 comprising lower conductive line 58 and 66 extend in a second Y-axis direction which is orthogonal to the first direction wherein the interfacial conductive pattern ICP also extends in the second direction), and
wherein a width of the interfacial conductive pattern in the first direction is greater than a width of the lower conductive line in the first direction (Nakamura, ICP, 58 and 66, annotated Fig. 9A depicts wherein the interfacial conductive pattern ICP has a width in the first X-axis direction greater than a width of the lower conductive line 58 and 66 in the first X-axis direction).
Regarding Claim 3, the combination of Nakamura, Sung and Sawabe discloses the semiconductor memory device of claim 2, wherein a side surface of the interfacial conductive pattern and a side surface of the channel structure are vertically aligned with each other (Nakamura, ICP, 26 and 30, annotated Fig. 9A depicts wherein a side surface of the interfacial conductive pattern ICP and a side surface of the channel structure 26 and 30 are vertically aligned with each other by being disposed on a sidewall of the gate insulating layer 36).
Regarding Claim 4, the combination of Nakamura, Sung and Sawabe discloses all the limitations of claim 1.
Nakamura and Sawabe fail to explicitly disclose the semiconductor memory device of claim 1, wherein the interfacial conductive pattern and the lower conductive line include a same material.
However, Sung teaches a similar semiconductor memory device, wherein the interfacial conductive pattern (111, Fig. 1D, para [0040] describes a barrier layer 111 at an interface between the channel structure 121 and a lower conductive line 110) and the lower conductive line include a same material (111, Fig. 1D, para [0040] describes wherein the interfacial conductive pattern 111 may comprise a material such as molybdenum and Nakamura teaches in para [0017] wherein the lower conductive line 58 and 66 may comprise a conductive material 58 such as molybdenum therefore the interfacial conductive pattern 111 of Sung and the lower conductive line 58 and 66 of Nakamura may comprise a same molybdenum material).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Nakamura, Sung and Sawabe to further disclose a semiconductor memory device wherein the interfacial conductive pattern and the lower conductive line include a same material in order to provide the well-known advantage of simplifying a manufacturing process by requiring a same metal material for subsequent device layers lowering manufacturing time and therefore reducing manufacturing costs.
Regarding Claim 5, the combination of Nakamura, Sung and Sawabe discloses the semiconductor memory device of claim 1, wherein a material of the interfacial conductive pattern and a material of the lower conductive line are different from each other (Nakamura, 28, ICP, 58 and 66, annotated Fig. 9A, para [0017] describes wherein the conductive material 58 of the lower conductive line 58 and 66 may comprise tungsten and molybdenum and para [0026] describes wherein the interfacial conductive pattern 28 and ICP may comprise indium, zinc and tin).
Regarding Claim 6, the combination of Nakamura, Sung and Sawabe discloses the semiconductor memory device of claim 1, wherein the channel structure (Nakamura, 26 and 30, Fig. 9A) comprises:
a horizontal channel portion in direct contact with the interfacial conductive pattern (Nakamura, HCP and 28, annotated Fig. 9A and annotated Fig. 9A II depicts a horizontal channel portion CHP in direct contact with the interfacial conductive pattern ICP); and
a vertical channel portion that extends in a vertical direction along a sidewall of the isolation insulating layer that defines the channel trench (Nakamura, VCP and 39, annotated Fig. 9A II depicts a vertical channel portion VCP that extends in a vertical Z direction along a sidewall of the isolation insulating layer 39 that defines the channel trench), and is in contact with the interfacial oxide semiconductor pattern (Nakamura and Sung, VCP and 28, annotated Fig. 9A II wherein upon combining Nakamura with Sung, the interfacial oxide semiconductor pattern 123 of Sung in direct contact with an upper surface of the channel 121 of Sung, would be in contact with an upper surface of the vertical channel portion VCP of Nakamura).
Regarding Claim 7, the combination of Nakamura, Sung and Sawabe discloses the semiconductor memory device of claim 6, wherein the first oxide semiconductor material of the channel structure has a first composition (Nakamura, 26, Fig. 9A, para [0025] describes wherein the semiconductor material 26 of the channel structure 26 and 30 may comprise a first composition such as InGaZnO), and
wherein the second oxide semiconductor material of the interfacial oxide semiconductor pattern has a second composition that is different from the first composition (Sung, 123, Fig. 1D, para [0045] describes wherein the interfacial oxide semiconductor 123 comprises a second oxide semiconductor material such as an indium-rich IGZO that would have a higher indium content than the composition of the IGZO oxide semiconductor material of the channel 121 such as the channel found in Nakamura therefore resulting in a different, second composition).
Regarding Claim 8, the combination of Nakamura, Sung and Sawabe discloses the semiconductor memory device of claim 7, wherein the second oxide semiconductor material comprises IGZO (InGaZnO), ITO (InSnO), IWO (InWO), IZO (InZnO), IGO (InGaO), ITGO (InSnGaO), IGSO (InGaSiO), or InO, or a combination of two or more thereof (Sung, 123, Fig. 1D, para [0045] describes wherein the interfacial oxide semiconductor 123 comprises a second oxide semiconductor material such as an indium-rich IGZO).
Regarding Claim 9, the combination of Nakamura, Sung and Sawabe discloses the semiconductor memory device of claim 7, wherein an indium content of the second oxide semiconductor material is greater than an indium content of the first oxide semiconductor material (Sung, 123, Fig. 1D, para [0045] describes wherein the interfacial oxide semiconductor 123 comprises a second oxide semiconductor material such as an indium-rich IGZO that would have a higher indium content than the content of the first oxide semiconductor material IGZO of the channel 121 such as the channel found in Nakamura).
Regarding Claim 17, Nakamura teaches a semiconductor memory device comprising:
a substrate (56, Fig. 9A, para [0049] describes a substrate 56);
a lower conductive line on the substrate (16, 58 and 66, Fig. 9A, para [0017] describes a conductive structure 16 comprising a conductive material 58 and a second conductive material 66);
a channel structure on the lower conductive line and comprising a first oxide semiconductor material (26 and 30, Fig. 9A, para [0022] describes a semiconductor material corresponding to a channel region 30 on the lower conductive line 58 and 66 wherein para [0025] describes the channel structure 26 may comprise an oxide semiconductor material);
a conductive contact pattern on the channel structure (74, Fig. 9A, para [0063] describes a conductive material 74 formed on the channel structure 26 and 30); and
a capacitor structure (14, Fig. 2A, para [0065] describes wherein storage elements, which may be capacitors as described in para [0016], are coupled to interconnects 50) comprising a lower electrode connected to the conductive contact pattern (50, Fig. 9A, para [0065] describes an interconnect structure 50 for a capacitor 14 connected to the conductive contact pattern 74).
Nakamura fails to explicitly disclose an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and comprising a second oxide semiconductor material.
However, Sung teaches a similar semiconductor memory device comprising an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern (123, 126 and 121 Fig. 1D, para [0031] describes an upper interface layer 123 comprised between a channel structure 121 and a conductive contact pattern 126 wherein the interfacial oxide semiconductor pattern 123 may comprise an oxide semiconductor interface layer) and comprising a second oxide semiconductor material (123, Fig. 1D, para [0041] describes wherein the interfacial oxide semiconductor pattern 123 may comprise a second oxide semiconductor pattern such as indium-rich IGZO).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Nakamura with Sung to further disclose a semiconductor memory device comprising an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and comprising a second oxide semiconductor material in order to provide the advantage of providing an interface material layer which may have a lower resistance than the channel layer in order to provide an ohmic contact between a channel and conductive contact and to enable a seamless interconnection of a channel material to a memory structure (Sung, para [0060]).
Nakamura and Sung fail to explicitly disclose wherein a contact area between the interfacial oxide semiconductor pattern and the conductive contact pattern is greater than a contact area between the interfacial oxide semiconductor pattern and the channel structure.
However, Sawabe teaches a similar semiconductor memory device, wherein a contact area between the interfacial oxide semiconductor pattern (62, Fig. 12, para [0095] describes an auxiliary layer 62 which may comprise a same oxide semiconductor material as the interfacial oxide semiconductor pattern of Sung, such as gallium oxide containing indium and zinc) and the conductive contact pattern (14, Fig. 12, para [0095] describes a drain electrode 14 comprising a conductive contact) is greater than a contact area between the interfacial oxide semiconductor pattern and the channel structure (62, 14 and 16, Fig. 12, para [0095] describes a channel layer structure 16 wherein a contact area between the interfacial oxide semiconductor pattern 62 and the conductive contact pattern 14 extends along an entire upper surface of the interfacial oxide semiconductor pattern 62 and wherein a contact area between the interfacial oxide semiconductor pattern 62 and channel structure 16 extends along a portion of a lower surface of the interfacial oxide semiconductor pattern 62).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Nakamura and Sung with Sawabe to further disclose a semiconductor memory device wherein a contact area between an interfacial oxide semiconductor pattern and a conductive contact pattern is greater than a contact area between the interfacial oxide semiconductor pattern and a channel structure in order to provide the advantage of providing an interfacial oxide semiconductor pattern which can reduce a resistance between an electrode and a channel layer so that an on-resistance of a device may be reduced therefore lowering operating costs.
Regarding Claim 20, the combination of Nakamura, Sung and Sawabe discloses the semiconductor memory device of claim 17, wherein each of the first oxide semiconductor material (Nakamura, 26, Fig. 9A, para [0025] describes wherein the first oxide semiconductor material 26 may comprise an indium metal oxide material such as InGaZnO) and the second oxide semiconductor material is a metal oxide semiconductor material containing indium (Sung, 123, Fig. 1D, para [0045] describes wherein the interfacial oxide semiconductor 123 comprises a second oxide semiconductor material such as an indium-rich IGZO), and
wherein an indium content of the second oxide semiconductor material is greater than an indium content of the first oxide semiconductor material (Sung, 123, Fig. 1D, para [0045] describes wherein the interfacial oxide semiconductor 123 comprises a second oxide semiconductor material such as an indium-rich IGZO that would have a higher indium content than the content of the first oxide semiconductor material IGZO of the channel 121 such as the channel found in Nakamura).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshitaka Nakamura et al. (US 2022/0059693 A1; hereinafter “Nakamura”) in view of Min Chul Sung (US 2023/0164977 A1; hereinafter “Sung”) in view of Tomoaki Sawabe et al. US 2019/0296155 A1; hereinafter “Sawabe”) and in further view of Tomoki Ishimaru et al. (US 2021/0305431 A1; hereinafter “Ishimaru”).
Regarding Claim 10, the combination of Nakamura, Sung and Sawabe teaches the semiconductor memory device of claim 6, wherein the interfacial oxide semiconductor pattern (Sawabe, 62, Fig. 12) comprises:
an upper pattern in contact with an upper surface of the isolation insulating layer and the conductive contact pattern (Sawabe, 62, Fig. 12, para [0100] describes an upper interfacial oxide semiconductor pattern 62 in contact with an upper surface of an isolation insulating layer 24 and the conductive contact pattern 14).
Nakamura and Sawabe fail to explicitly disclose wherein the interfacial oxide semiconductor pattern comprises: a lower pattern that extends along the sidewall of the isolation insulating layer and is in contact with a top of the channel structure; and an upper pattern that is arranged on the lower pattern, and wherein a width of the upper pattern is greater than a width of the lower pattern, in a second direction in which the lower conductive line extends.
However, Ishimaru teaches a similar semiconductor memory device, wherein the interfacial oxide semiconductor pattern (16, Fig. 20, para [0156] describes a region 16 that is an oxide semiconductor on a channel structure 18) comprises:
a lower pattern that extends along the sidewall of the isolation insulating layer and is in contact with a top of the channel structure (LP, annotated Fig. 20 depicts lower patterns LP of the interfacial oxide semiconductor material 16 that extend along a sidewall of an isolation insulating material 28 and are in contact with a top of channel structure 18); and
an upper pattern that is arranged on the lower pattern (UP, annotated Fig. 20 depicts an upper pattern UP on the lower patterns LP), and
wherein a width of the upper pattern is greater than a width of the lower pattern, in a second direction in which the lower conductive line extends (UP and LP, annotated Fig. 20 depicts wherein a width of the upper pattern extends an entire length of the channel structure 18 having a width in a second direction (first direction from annotated Fig. 20) in which the lower conductive line extends that is greater than a width of the lower pattern LP which does not extend along a length of channel portion 18b in the second direction).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Nakamura, Sung and Sawabe with Ishimaru to disclose a semiconductor memory device wherein an interfacial oxide semiconductor pattern comprises a lower pattern that extends along a sidewall of an isolation insulating layer and is in contact with a top of a channel structure; and an upper pattern that is arranged on the lower pattern, and wherein a width of the upper pattern is greater than a width of the lower pattern, in a second direction in which a lower conductive line extends in order to provide the advantage of providing an interfacial oxide semiconductor pattern which is conformal to a channel structure comprising a core portion and a surface portion which reduces an off-leakage current therefore increasing device reliability (Ishimaru, para [0204]).
Regarding Claim 11, the combination of Nakamura, Sung, Sawabe and Ishimaru teaches the semiconductor memory device of claim 10, wherein a side surface of the upper pattern is vertically aligned with a side surface of the conductive contact pattern (Sawabe, 62 and 14, Fig. 12, para [0099] describes interfacial oxide semiconductor pattern 62 which comprises an upper pattern in contact with an upper surface of an isolation insulating layer 24 and the conductive contact pattern 14 wherein a side surface of the upper pattern 62 is vertically aligned with a side surface of the conductive contact pattern 14 as shown in Fig. 12).
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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