DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0294998 A1 to Lilak et al. (hereinafter “Lilak”).
Regarding claim 1, Lilak discloses a semiconductor device (IC having stacked transistor configuration which may comprise any number of fin structures and gate structures within upper and lower device regions 104, 108; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]) comprising:
a first transistor comprising a first source/drain region disposed on a side of the first transistor (lower device region 104 having source/drain region 124A of a first transistor on a side thereof; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]);
a second transistor comprising a second source/drain region disposed on a side of the second transistor (lower device region 104 having source/drain region 124A of a second transistor on a side thereof; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]);
a first source/drain contact disposed under the first source/drain region, wherein sidewalls of the first source/drain contact are aligned with sidewalls of the first source/drain region (first backside source/drain contact 138 disposed under first source/drain region 124A with aligned sidewalls; Fig. 1A; paragraph [0013]); and
a second source/drain contact disposed under the second source/drain region, wherein a dimension of the second source/drain contact is larger than a dimension of the second source/drain region such that at least one sidewall of the second source/drain contact is out of alignment with at least one sidewall of the second source/drain region (second backside source/drain contact 138 comprising extension interconnect feature 128 disposed under second source/drain region 124A with sidewalls not aligned given overlap regions 144; Fig. 1A; paragraphs [0013], [0028]);
wherein the second transistor comprises a plurality of channel layers in proximity to a dielectric layer of a gate cut portion (nanowires 116A of second transistor disposed in proximity to insulation material 332 layer made from materials able to support an electrostatic field and exhibit a dielectric constant, where material 332 layer is part of isolation structure 324 disposed between gate structures; Figs. 3A-3B; paragraph [0045]).
Lilak fails to disclose a plurality of channel layers contacting a dielectric layer of a gate cut portion.
However, Lilak already discloses the channel layers being disposed in proximity to the dielectric layer and so it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lilak to have the channel layers directly contact the dielectric layer in order to potentially provide tighter device-to-device spacing, improved electrical isolation, and reduced parasitic coupling.
Regarding claim 2, Lilak discloses the semiconductor device of claim 1, further comprising: a third transistor stacked on the first transistor and comprising a third source/drain region disposed on a side of the third transistor, wherein the third source/drain region is stacked on the first source/drain region (third transistor of upper device region 108 having source/drain region 124B stacked upon first source/drain region 124A; Fig. 1A; paragraph [0013]); and a fourth transistor stacked on the second transistor and comprising a fourth source/drain region disposed on a side of the fourth transistor, wherein the fourth source/drain region is stacked on the second source/drain region (fourth transistor of upper device region 108 having source/drain region 124B stacked upon second source/drain region 124A; Fig. 1A; paragraph [0013]).
Regarding claim 3, Lilak discloses the semiconductor device of claim 2, further comprising a via disposed along a side of the fourth source/drain region and the second source/drain region, wherein the at least one sidewall of the second source/drain contact contacts a sidewall of the via (buried conductor 328 formed by structure 324 disposed along sides of source/drain regions 124 and in contact with sidewalls of where backside contacts are formed in region 356; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 4, Lilak discloses the semiconductor device of claim 3, wherein the dielectric layer of the gate cut portion is disposed between the fourth source/drain region and the via, and between the second source/drain region and the via (material 332 layer disposed between regions 124B and conductor 328 and between regions 124A and conductor 328; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 5, Lilak discloses the semiconductor device of claim 3, wherein the fourth transistor comprises a plurality of channel layers in proximity to the dielectric layer of the gate cut portion (nanowires 116B of fourth transistor disposed in proximity to material 332 layer; Figs. 3A-3B; paragraph [0045]).
Lilak fails to disclose a plurality of channel layers contacting a dielectric layer of a gate cut portion.
However, Lilak already discloses the channel layers being disposed in proximity to the dielectric layer and so it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lilak to have the channel layers directly contact the dielectric layer in order to potentially provide tighter device-to-device spacing, improved electrical isolation, and reduced parasitic coupling.
Regarding claim 6, Lilak discloses the semiconductor device of claim 5, the dielectric layer of the gate cut portion is disposed between the via and the plurality of channel layers of the second transistor and between the via and the plurality of channel layers of the fourth transistor (material 332 layer disposed between nanowires 116B and conductor 328 and between nanowires 116A and conductor 328; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 7, Lilak discloses the semiconductor device of claim 3, wherein: the via is connected to a voltage source disposed on a first side of the semiconductor device (buried conductor 328 may be electrically connected to a vertical interconnect which is electrically connected to frontside local contacts 125 and BEOL metallization layers M0-Mn which is the conventional way power and signals are delivered in ICs; Figs. 1A-1B, 3A-3B; paragraphs [0013], [0029], [0054]); and the first and the second source/drain contacts are disposed on a second side of the semiconductor device opposite the first side (contacts 138 and interconnect 128 disposed in backside contact region 103; Fig. 1A).
Regarding claim 8, Lilak discloses the semiconductor device of claim 7, wherein the first source/drain contact is connected to a voltage source disposed on the second side of the semiconductor device (backside contact region 103 including contacts 138 may utilize interconnects for connecting to voltage source to route power; Fig. 1A; paragraphs [0013], [0029], [0054]).
Regarding claim 9, Lilak discloses the semiconductor device of claim 1, wherein the first and the second source/drain contacts are disposed in a dielectric layer, and the first source/drain contact is disposed at a greater depth in the dielectric layer than the second source/drain contact (first contact 138 is disposed on average deeper within layer of dielectric materials 126, 136, 140 than second contact 138 with interconnect structure 128 which extends out of the dielectric layer; Fig. 1A).
Regarding claim 10, Lilak discloses the semiconductor device of claim 1, wherein the first transistor comprises a gate-all-around transistor, and the second transistor comprises a forksheet transistor (transistors may be gate-all-around transistors and may utilize centrally-disposed isolation wall structures as in a forksheet transistor; paragraphs [0008], [0029], [0042]).
Regarding claim 11, Lilak discloses a semiconductor device (IC having stacked transistor configuration which may comprise any number of fin structures and gate structures within upper and lower device regions 104, 108; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]) comprising:
a first transistor comprising a first source/drain region disposed on a side of the first transistor (lower device region 104 having source/drain region 124A of a first transistor on a side thereof; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]);
a second transistor stacked on the first transistor and comprising a second source/drain region disposed on a side of the second transistor, wherein the second source/drain region is stacked on the first source/drain region (second transistor of upper device region 108 having source/drain region 124B stacked upon first source/drain region 124A; Fig. 1A; paragraph [0013]); and
a source/drain contact disposed under the first source/drain region, wherein a dimension of the source/drain contact is larger than a dimension of the first source/drain region such that at least one sidewall of the source/drain contact is out of alignment with at least one sidewall of the first source/drain region (first backside source/drain contact 138 comprising extension interconnect feature 128 disposed under second source/drain region 124A with sidewalls not aligned given overlap regions 144; Fig. 1A; paragraphs [0013], [0028]);
wherein the first transistor comprises a plurality of channel layers in proximity to a dielectric layer of a gate cut portion (nanowires 116A of first transistor disposed in proximity to insulation material 332 layer made from materials able to support an electrostatic field and exhibit a dielectric constant, where material 332 layer is part of isolation structure 324 disposed between gate structures; Figs. 3A-3B; paragraph [0045]).
Lilak fails to disclose a plurality of channel layers contacting a dielectric layer of a gate cut portion.
However, Lilak already discloses the channel layers being disposed in proximity to the dielectric layer and so it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lilak to have the channel layers directly contact the dielectric layer in order to potentially provide tighter device-to-device spacing, improved electrical isolation, and reduced parasitic coupling.
Regarding claim 12, Lilak discloses the semiconductor device of claim 11, further comprising a via disposed along a side of the second source/drain region and the first source/drain region, wherein the at least one sidewall of the source/drain contact contacts a sidewall of the via (buried conductor 328 formed by structure 324 disposed along sides of source/drain regions 124 and in contact with sidewalls of where backside contacts are formed in region 356; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 13, Lilak discloses the semiconductor device of claim 12, wherein the dielectric layer of the gate cut portion is disposed between the second source/drain region and the via, and between the first source/drain region and the via (material 332 layer disposed between regions 124B and conductor 328 and between regions 124A and conductor 328; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 14, Lilak discloses the semiconductor device of claim 12, wherein the second transistor comprises a plurality of channel layers in proximity to the dielectric layer of the gate cut portion, wherein the dielectric layer of the gate cut portion is disposed between the via and the plurality of channel layers of the second transistor (nanowires 116B of fourth transistor disposed in proximity to material 332 layer which itself is disposed between nanowires 116B and conductor 328; Figs. 3A-3B; paragraph [0045]).
Lilak fails to disclose a plurality of channel layers contacting a dielectric layer of a gate cut portion.
However, Lilak already discloses the channel layers being disposed in proximity to the dielectric layer and so it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lilak to have the channel layers directly contact the dielectric layer in order to potentially provide tighter device-to-device spacing, improved electrical isolation, and reduced parasitic coupling.
Regarding claim 15, Lilak discloses the semiconductor device of claim 12, wherein: the via is connected to a voltage source disposed on a first side of the semiconductor device (buried conductor 328 may be electrically connected to a vertical interconnect which is electrically connected to frontside local contacts 125 and BEOL metallization layers M0-Mn which is the conventional way power and signals are delivered in ICs; Figs. 1A-1B, 3A-3B; paragraphs [0013], [0029], [0054]); and the source/drain contact is disposed on a second side of the semiconductor device opposite the first side (contacts 138 and interconnect 128 disposed in backside contact region 103; Fig. 1A).
Regarding claim 16, Lilak discloses the semiconductor device of claim 11, wherein the plurality of channel layers in proximity to the dielectric layer of the gate cut portion where the at least one sidewall of the source/drain contact is out of alignment with the at least one sidewall of the first source/drain region (nanowires 116A disposed in proximity to insulation material 332 layer in region where contact 138 with interconnect structure 128 is disposed; Figs. 1A-1B, 3A-3B).
Lilak fails to disclose a plurality of channel layers contacting a dielectric layer of a gate cut portion.
However, Lilak already discloses the channel layers being disposed in proximity to the dielectric layer and so it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lilak to have the channel layers directly contact the dielectric layer in order to potentially provide tighter device-to-device spacing, improved electrical isolation, and reduced parasitic coupling.
Regarding claim 17, Lilak discloses a semiconductor device comprising:
a stacked structure comprising a plurality of gate structures alternately stacked with a plurality of channel layers (IC having stacked transistor configuration which may comprise any number of fin structures and gate structures within upper and lower device regions 104, 108, where gates 120 are alternately stacked with nanowires 116; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]);
at least one source/drain region disposed on a side of the stacked structure (lower device region 104 having source/drain region 124A on a side of alternately stacked nanowires 116 and gates 120; Fig. 1A; paragraphs [0013], [0015], [0027], [0096]); and
a source/drain contact disposed under the at least one source/drain region, wherein a dimension of the source/drain contact is larger than a dimension of the at least one source/drain region such that at least one sidewall of the source/drain contact is out of alignment with at least one sidewall of the at least one source/drain region (backside source/drain contact 138 comprising extension interconnect feature 128 disposed under second source/drain region 124A with sidewalls not aligned given overlap regions 144; Fig. 1A; paragraphs [0013], [0028]);
wherein the plurality of channel layers in proximity to a dielectric layer of a gate cut portion (nanowires 116 disposed in proximity to insulation material 332 layer made from materials able to support an electrostatic field and exhibit a dielectric constant, where material 332 layer is part of isolation structure 324 disposed between gate structures; Figs. 3A-3B; paragraph [0045]).
Lilak fails to disclose a plurality of channel layers contacting a dielectric layer of a gate cut portion.
However, Lilak already discloses the channel layers being disposed in proximity to the dielectric layer and so it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lilak to have the channel layers directly contact the dielectric layer in order to potentially provide tighter device-to-device spacing, improved electrical isolation, and reduced parasitic coupling.
Regarding claim 18, Lilak discloses the semiconductor device of claim 17, further comprising a via disposed along a side of the at least one source/drain region, wherein the at least one sidewall of the source/drain contact contacts a sidewall of the via (buried conductor 328 formed by structure 324 disposed along sides of source/drain regions 124 and in contact with sidewalls of where backside contacts are formed in region 356; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 19, Lilak discloses the semiconductor device of claim 18, wherein the dielectric layer of the gate cut portion is disposed between the at least one source/drain region and the via (material 332 layer disposed between regions 124 and conductor 328; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Regarding claim 20, Lilak discloses the semiconductor device of claim 18, wherein the dielectric layer of the gate cut portion is disposed between the via and the plurality of gate structures and the plurality of channel layers (material 332 layer disposed between conductor 328 and gate electrodes 120 and nanowires 116; Figs. 1A-1B, 3A-3B, 6E-6F; paragraphs [0026], [0029], [0045], [0054]).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2016/0056249 A1 to Kleemeier et al. and US 2022/0293750 A1 to Cheng disclose stacked semiconductor devices with backside contacts having related structures and functionalities.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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