DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1, Modification A1, claims 1-4, 6-9, and 11-17 in the reply filed on 5/11/2026 is acknowledged. The traversal is on the ground(s) that search can be made without serious burden. This is not found completely persuasive because each species and modification would require separate search strategies. Considering the species, the examiner would have to search for a junction element connected to the high dopant region or the low dopant region of the third layer or is connected with the low and high dopant regions of the second and third layers, where each region has different keywords. The junction element itself is broad and can be considered a conductor in electrical contact with each layer.
Regarding the Modifications A1 and A2, the examiner agrees that restriction is improper and the restriction requirement is withdrawn.
Regarding the Modifications B1 and B2, although the features are not claimed, they mutually exclusive and would require different strategies to search if incorporated from the specification into the claims.
The requirement is still deemed proper and is therefore made FINAL.
Claim 10 is withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 5/11/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 8, 11, 13-15 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et at. US 20170309612 A1 (hereinafter referred to as Lin).
Regarding claim 1, Lin teaches
A semiconductor device (“silicon controlled rectifier 100” para. 0026 FIG. 1) comprising:
a first layer (“first semiconductor region 141” para. 0026) doped with a first type of charge carriers (“first semiconductor region 141” is shown as p-type);
a second layer (“first semiconductor well 110” and “third semiconductor region 143”, para. 0027-0028) doped with a second type of charge carriers different from the first type of charge carriers (“first semiconductor well 110” and “third semiconductor region 143” are n-type, para.0027-0028);
a third layer doped with the first type of charge carriers (p-type “fourth semiconductor region 144” and “second semiconductor well 120” para. 0027-0028);
a fourth layer doped with the second type of charge carriers (n-type “second semiconductor region 142”), wherein the first, second, third and fourth layers form a Shockley diode (though not explicitly stated, the examiner understands the arrangement of doped layers forms a Shockley diode analogous to how the layers in FIG. 3A of Holland et al. US 20180145065 A1 form a Shockley diode);
an input terminal (“first pad 161” para. 0026) electrically connected with the first layer; and
an output terminal (“second pad 162” para. 0026) electrically connected with the fourth layer;
wherein the first, second and third layers form a bipolar junction transistor (BJT) (the examiner understands that “first semiconductor region 141”, “first semiconductor well 110” and “third semiconductor region 143”, and “fourth semiconductor region 144” form a pnp BJT), and the second, third and fourth layers form a second BJT (the examiner understands that “third semiconductor region 143”, “fourth semiconductor region 144” and “second semiconductor well 120”, and “second semiconductor region 142” form an npn BJT), wherein the second layer has a junction element electrically connected to the third layer (“silicide layer 150” para. 0026), wherein the third layer comprises a high dopant region (“fourth semiconductor region 144” is shown as being P+, which is understood as being heavily doped p-type just as “third semiconductor region 143” is described as a heavily doped n-type region and being designated as n+, para. 0028) adjoining the second layer, and wherein the junction element is a short (“silicide layer 150” is a conductor, para. 0029, such that it is understood to short “third and fourth semiconductor regions 143 and 144”).
Regarding claim 2, Lin teaches the semiconductor device according to claim 1, wherein the third layer comprises a low dopant region adjoining the high dopant region of the third layer (“second semiconductor well 120” is understood to be less doped than “fourth semiconductor region 144” it adjoins) as well as adjoining the fourth layer (“second semiconductor well 120” adjoins the “second semiconductor layer 142”, para. 0030), and wherein the doping of the high dopant region is higher than the doping of the low dopant region. (because “second semiconductor well 120” is a well region and “fourth semiconductor region 144” is designated with P+, the examiner understands “fourth semiconductor region 144” is higher doped than “second semiconductor well 120”.)
Regarding claim 4, Lin teaches the semiconductor device according to claim 1, wherein the first type of charge carriers are P-type carriers (“first and fourth semiconductor regions 141 and 144” and “second semiconductor well 120” are p-type, the first type of charge carrier), and wherein the second type of charge carriers are N-type carriers (“first semiconductor well 110” and “third semiconductor region 143” and “second semiconductor region 142” are n-type, the second type of charge carrier).
Regarding claim 8, Lin teaches the semiconductor device according to claim 1, wherein the first layer is formed as a well in the second layer (“first semiconductor region 141” is formed in “semiconductor well 110”, para. 0028).
Regarding claim 11, Lin teaches the semiconductor device according to claim 2, wherein the second layer comprises a high dopant region adjoining the high dopant region of the third layer (“third semiconductor region 143” of second layer adjoins “fourth semiconductor region 144” of third layer) and a low dopant region adjoining the first layer (“second semiconductor well 110” of second layer adjoins “first semiconductor region 141”), and wherein the doping of the high dopant region is higher than the doping of the low dopant region (“third semiconductor region 143” is a heavily doped n-type region designated as p+, para. 0028, while “first semiconductor well 110” is understood to have less dopant).
Regarding claim 13, Lin teaches the semiconductor device according to claim 2, wherein the fourth layer is formed as a well in the low dopant region of the third layer (“second semiconductor region 142” is formed in “second semiconductor well 120”, the low dopant part of the third region.)
Regarding claim 14, Lin teaches the semiconductor device according to claim 2, wherein the high dopant region of the third layer is formed as a well in the low dopant region of the third layer (“fourth semiconductor region 144” is formed in “second semiconductor well 120”).
Regarding claim 15, Lin teaches the semiconductor device according to claim 2, wherein the first layer has a doping higher than the doping the low dopant region of the third layer (“first semiconductor region 141” is shown as being P+, which is understood as being heavily doped p-type, while “second semiconductor well 120” is understood to have less dopant).
Regarding claim 17, Lin teaches the semiconductor device according to claim 2, wherein the first type of charge carriers are P-type carriers (“first and fourth semiconductor regions 141 and 144” and “second semiconductor well 120” are p-type, the first type of charge carrier), and wherein the second type of charge carriers are N-type carriers (“first semiconductor well 110” and “third semiconductor region 143” and “second semiconductor region 142” are n-type, the second type of charge carrier).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, as applied to claim 1 above, in view of Narita US 5717559 A (hereinafter referred to as Narita).
Regarding claim 3, Lin teaches the semiconductor device according to claim 1 but fails to teach wherein the third layer comprises a low dopant region adjoining the high dopant region of the third layer as well as adjoining the fourth layer, and wherein the doping of the high dopant region is higher than the doping of the low dopant region.
Nevertheless, Narita teaches a similar thyristor device where the “N-type diffused region 50” that connects to ground is formed within an “N-well 70” having less dopant (col 7 lines 15-20 FIG. 3). “N-well 70” lowers the potential required for current to flow from the P-type “substrate 1” to the “N-well 70” and reduces the resistance (col 8 lines 32-40). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that forming “second semiconductor region 142” in a lower doped region such as “N-well 70” will reduce the potential for current to flow from the P-type “second semiconductor well 120” into “second semiconductor region 142”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Lin with the fourth layer as taught in Narita. By having the low dopant region adjoining the third layer, the potential required for the second BJT to activate is reduced.
Regarding claim 16, Lin teaches the semiconductor device according to claim 2 but fails to teach wherein the fourth layer comprises a high dopant region adjoining the output terminal and a low dopant region adjoining the third layer, and wherein the doping of the high dopant region is higher than the doping of the low dopant region.
Nevertheless, Narita a similar thyristor device where the “N-type diffused region 50” that connects to ground is formed within an “N-well 70” having less dopant (col 7 lines 15-20 FIG. 3). “N-well 70” lowers the potential required for current to flow from the P-type “substrate 1” to the “N-well 70” and reduces the resistance (col 8 lines 32-40). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that forming “second semiconductor region 142” in a lower doped region such as “N-well 70” will reduce the potential for current to flow from the P-type “second semiconductor well 120” into “second semiconductor region 142”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Lin with the fourth layer as taught in Narita. By having the low dopant region adjoining the third layer, the potential required for the second BJT to activate is reduced.
Claim 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 1, in view of Ritter US 20160268447 A1 (hereinafter referred to as Ritter).
Regarding claim 5, Lin teaches the semiconductor device according to claim 1 but fails to teach wherein the first type of charge carriers are N-type carriers, and wherein the second type of charge carriers are P-type carriers.
Nevertheless, Ritter shows the use a forward biased “Shockley diode 104” in FIG. 1 and “Shockley diode 204” in FIG. 2 comprising a PNPN layer arrangement in data transmission systems (para. 0037-0044). These Shockley diodes trigger for currents positive respect to ground (para. 0039). Meanwhile, FIG. 3 shows the incorporation of a “Shockley diode 312” with a NPNP layer arrangement that can trigger for negative currents on the signal line (para. 0045). This shows that a Shockley diode in NPNP can protect and electrostatic discharge for negative currents. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that inverting the charge type of the layers in Lin would allow the “silicon controlled rectifier 100” to trigger for negative currents.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Lin with the charge carriers as taught in Ritter. The choice of charge type determines if the semiconductor device triggers for a positive or negative surge current.
Regarding claim 18, Lin teaches the semiconductor device according to claim 2 but fails to teach wherein the first type of charge carriers are N-type carriers, and wherein the second type of charge carriers are P-type carriers.
Nevertheless, Ritter shows the use a forward biased “Shockley diode 104” in FIG. 1 and “Shockley diode 204” in FIG. 2 comprising a PNPN layer arrangement in data transmission systems (para. 0037-0044). These Shockley diodes trigger for currents positive respect to ground (para. 0039). Meanwhile, FIG. 3 shows the incorporation of a “Shockley diode 312” with a NPNP layer arrangement that can trigger for negative currents on the signal line (para. 0045). This shows that a Shockley diode in NPNP can protect and electrostatic discharge for negative currents. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that inverting the charge type of the layers in Lin would allow the “silicon controlled rectifier 100” to trigger for negative currents.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Lin with the charge carriers as taught in Ritter. The choice of charge type determines if the semiconductor device triggers for a positive or negative surge current.
Claim 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 1, in view of Chen et al. US 20130181211 A1 (hereinafter referred to as Chen), in view of Miniaturization Problems in CMOS Technology: Investigation of Doping Profiles and Reliability by Robert Wittmann (hereinafter referred to as Wittmann).
Regarding claim 6, Lin teaches the semiconductor device according to claim 1 but fails to teach wherein the high dopant region has a doping greater than 1x1015 cm3 and a layer thickness greater than 0.2 µm.
Nevertheless, Chen teaches a similar device with two “bipolar junction transistors Q1 and Q2” (para. 0045 FIG. 1B) where a “P-type first heavily doped region 108” and P-type second heavily doped region 112” are implanted to a depth of 200nm at a concentration of 4x1015/cm2 (para. 0038 and 0040). It is known that implant concentration affects the electron or hole concentration in a semiconductor material and the material’s resistance, as evidenced in “2.Semiconductor Doping Technology” in Wittmann. Furthermore, it is known that the implant depth predominantly depends on the energy of the ion and low energy high concentration doping is typical or forming shallow junctions, as evidenced in “2.2.3 Process Parameters for Ion Implantation” of Wittmann. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the dopant concentration and the depth of “fourth semiconductor region 144” in Lin depends on the desired conductive performance and the energy with which it is implanted.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Lin with the doping concentration and depth as taught in Chen and Wittmann. The concentration of the high dopant region determines the available holes for conduction and the depth depends on the energy with which they are implanted.
Furthermore, the instant application specification contains no disclosure of either the critical nature of the claimed concentration and thickness i.e., “a doping greater than 1x1015 cm3 and a layer thickness greater than 0.2 µm” or of any unexpected results arising therefrom. Applicant has not disclosed that having [the claimed feature] solves any stated problem or is for any particular purpose. "Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies." - In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946), see MPEP 2144.05.III.A.
Where patentability is said to be based upon particular chosen dimensions, alignment, positioning, or upon another variable recited in a claim, the applicant must show that the chosen dimensions or values are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).). In view of the above, inter alia, the limitation of “a doping greater than 1x1015 cm3 and a layer thickness greater than 0.2 µm” is not patentable over Lin, in view of Chen and Wittmann.
Regarding claim 12, Lin teaches the semiconductor device according to claim 2 but fails to teach wherein the high dopant region has a doping greater than 1x1015 cm3 and a layer thickness greater than 0.2 µm.
Nevertheless, Chen teaches a similar device with two “bipolar junction transistors Q1 and Q2” (para. 0045 FIG. 1B) where a “P-type first heavily doped region 108” and P-type second heavily doped region 112” are implanted to a depth of 200nm at a concentration of 4x1015/cm2 (para. 0038 and 0040). It is known that implant concentration affects the electron or hole concentration in a semiconductor material and the material’s resistance, as evidenced in “2.Semiconductor Doping Technology” in Wittmann. Furthermore, it is known that the implant depth predominantly depends on the energy of the ion and low energy high concentration doping is typical or forming shallow junctions, as evidenced in “2.2.3 Process Parameters for Ion Implantation” of Wittmann. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the dopant concentration and the depth of “fourth semiconductor region 144” in Lin depends on the desired conductive performance and the energy with which it is implanted.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught in Lin with the doping concentration and depth as taught in Chen and Wittmann. The concentration of the high dopant region determines the available holes for conduction and the depth depends on the energy with which they are implanted.
Furthermore, the instant application specification contains no disclosure of either the critical nature of the claimed concentration and thickness i.e., “a doping greater than 1x1015 cm3 and a layer thickness greater than 0.2 µm” or of any unexpected results arising therefrom. Applicant has not disclosed that having [the claimed feature] solves any stated problem or is for any particular purpose. "Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies." - In re Scherl, 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946), see MPEP 2144.05.III.A.
Where patentability is said to be based upon particular chosen dimensions, alignment, positioning, or upon another variable recited in a claim, the applicant must show that the chosen dimensions or values are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).). In view of the above, inter alia, the limitation of “a doping greater than 1x1015 cm3 and a layer thickness greater than 0.2 µm” is not patentable over Lin, in view of Chen and Wittmann.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 1, in view of Holland et al. US 20180145065 A1 (hereinafter referred to as Holland).
Lin teaches the semiconductor device according to claim 1 but fails to teach further comprising an oxide substrate on which the third layer is deposited.
Nevertheless, Holland taches
further comprising an oxide substrate on which the third layer is deposited (“region 312” in “p- region 310” are disposed on “oxide 304”, para. 0047 FIG. 3A).
Lin and Holland teach Shockley diodes. While the doped layers in Lin are formed on a p-type “semiconductor substrate 130” (Lin para. 0026), the layers in Holland are formed over an “oxide 304” so that the layers are isolated from the lightly doped “substrate 302” (Holland para. 0047). The examiner understands this can confine the active area of the Shockley diode and avoid stray currents or punch-through into “substrate 302”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “oxide 304” can be used to isolate the Shockley diode from the “semiconductor substrte130”, as done in “silicon-on-insulator” technology.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Lin with the oxide layer taught in Holland. The oxide layer isolates the doped layers of the Shockley diode from the underlying substrate.
Allowable Subject Matter
Claim 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The most relevant prior art Lin teaches the second layer “first semiconductor well 110” and “third semiconductor region 143” formed within a p-type “semiconductor substrate 130”. However, the concentration is not specified and one of ordinary skill in the art would understand the concentration to be lower than those designated as P+. Lin fails to teach or render obvious wherein the second layer is formed as a well in the high dopant region of the third layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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