DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1 in the reply filed on 09 March 2026 is acknowledged. The traversal is on the ground(s) that there is no serious burden on the Examiner to search and examine all claims drawn to the unique species. This is not found persuasive because the unique species requires a multitude of additional search strategies and consideration of a multitude of additional prior art, as searching one species with its unique features is unlikely to populate results to unique features of the other species.
The requirement is still deemed proper and is therefore made FINAL. Claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-14, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hyesung Park et al. (US 20200402982 A1; hereinafter Park) in view of Eun Jeong Kim et al. (US 20230328960 A1; hereinafter Kim).
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Regarding Claim 1, Park discloses a semiconductor device (Fig. 1, 2, 3A, 3B), comprising:
a substrate (5; ¶0018) including a cell region (A; ¶0019) and a peripheral circuit region (B; ¶0019);
a first gate structure (80; ¶0021) in the cell region (A) of the substrate (5), the first gate structure (80) extending in a first direction (II-II’ direction) parallel to an upper surface of the substrate;
bit line structures (140; ¶0023) on the cell region (A) of the substrate (5), the bit line structures (140) extending in a second direction (III-III’ direction) perpendicular to the first direction and parallel to the upper surface of the substrate;
a second gate structure (120; ¶0024) on the peripheral circuit region (B) of the substrate (5);
contact plug structures (180A comprising 181+189; ¶0032) between the bit line structures (140), the contact plug structures (180A) contacting the substrate (impurity regions 15b of substrate 5; Fig. 3A; ¶0032);
first conductive structures (180B; ¶0033) on the peripheral circuit region (B) of the substrate (5), the first conductive structures (180B) being electrically connected to the peripheral circuit region of the substrate (via 133; ¶0030; Fig. 3B);
a first upper insulation structure (202b; ¶0039) between the first conductive structures (180B) (Fig. 3B), the first upper insulation structure including a first upper insulation pattern (material of 202b); and
a second upper insulation pattern (202a; ¶0039) between upper portions of the contact plug structures (180A).
Park is silent regarding wherein the first upper insulation structure (202b) further includes a hydrogen diffusing insulation pattern surrounding a bottom and sidewalls of the first upper insulation pattern.
In the same field of endeavor, Kim teaches a similar DRAM device (Fig. 1B; ¶0063) similarly comprising: a second gate structure on a peripheral region (45 of peripheral transistor 40; ¶0024; ¶0041) and upper insulation structure (70p; ¶0045) including a hydrogen diffusing insulation pattern (SiBN layer 71p; ¶0045; this limitation is intended use and therefore the material being the same as what is recited in the specification and claims satisfies this limitation, MPEP 2114) surrounding a bottom and sidewalls of a first upper insulation pattern (72P; ¶0045).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the upper insulation structure of Kim for that of Park in order to achieve good electrical insulation of peripheral interconnections while providing a higher etch resistance (Park; ¶0045, ¶0047, ¶0048).
Regarding Claim 2, modified Park teaches the semiconductor device of claim 1, wherein the hydrogen diffusing insulation pattern (Kim; SiBN 71P; ¶0045) includes a material having a hydrogen diffusivity higher than a hydrogen diffusivity of silicon nitride (as 71P includes a same material as in the instant specification this limitation is satisfied).
Regarding Claim 3, modified Park teaches the semiconductor device of claim 2, wherein the hydrogen diffusing insulation pattern includes at least one of SiCN, SiBN, or SiO2 (71P is SiBN; ¶0045).
Regarding Claim 4, modified Park teaches the semiconductor device of claim 1, wherein the first upper insulation pattern (202b/ Kim 72p) and the second upper insulation pattern (202a / Kim 72c) include silicon nitride (collectively 202; contain SiN; ¶0124; similarly as modified by Kim; 72p; ¶0045, ¶0030).
Regarding Claim 5, modified Park teaches the semiconductor device of claim 1, further comprising:
an insulating interlayer (139; ¶0025) on the peripheral circuit region (B) of the substrate, the insulating interlayer (139) covering the second gate structure (120);
the insulating interlayer including silicon oxide (¶0069);
a first capping layer (142b; ¶0070) on the peripheral circuit region (B) of the substrate, the first capping layer (142b) covering the insulating interlayer (139); and
the first capping layer including silicon nitride (¶0071),
wherein at least a portion of the hydrogen diffusing insulation pattern (as modified, 70p of Kim including 71p surrounding a bottom and sidewalls of 72p, as the 202b of Park) in the first upper insulation structure directly contacts the insulating interlayer (139) (wherein Kim’s 70p as the 202b of Park would result in Kim’s 71p directly contacting 139; as shown in Park Fig. 3B).
Regarding Claim 6, modified Park teaches the semiconductor device of claim 1, further comprising:
an etch stop layer (204; ¶0043) on the first conductive structures (180B), the first upper insulation structure (modified 202b), the contact plug structures (180A), and the second upper insulation pattern (202a) (as shown in Park Fig. 3A and 3B); and
a cell capacitor (210; ¶0042) on the cell region (A) of the substrate, the cell capacitor passing through the etch stop layer (204) and contacting the contact plug structures (180A) (as shown in Fig. 3A; ¶0043).
Regarding Claim 9, modified Park teaches the semiconductor device of claim 1, wherein the bit line structures (140) include a conductive pattern (Fig. 3A; 121a; ¶0023) and a capping pattern (145; ¶0023), and a spacer structure (154/157; ¶0041) is further on sidewalls of the bit line structures (140).
Regarding Claim 10, modified Park teaches the semiconductor device of claim 9, wherein a bottom of the second upper insulation pattern (bottom of 202a) is lower than an uppermost surface of the bit line structures (top most portion of 140), and a lower portion of the second upper insulation pattern (lower portion of 202a) contacts the capping pattern (145) and the spacer structure (154/157) (as shown in Fig. 3A).
Regarding Claim 11, Park discloses a semiconductor device (Fig. 1, 2, 3A, 3B), comprising:
a substrate (5; ¶0018) including a cell region (A; ¶0019) and a peripheral circuit region (B; ¶0019);
a first gate structure (80; ¶0021) in the cell region (A) of the substrate (5), the first gate structure (80) extending in a first direction (II-II’ direction) parallel to an upper surface of the substrate;
bit line structures (140; ¶0023) on the cell region (A) of the substrate (5), the bit line structures (140) extending in a second direction (III-III’ direction) perpendicular to the first direction and parallel to the upper surface of the substrate;
a second gate structure (120; ¶0024) on the peripheral circuit region (B) of the substrate (5);
an insulating interlayer (139; ¶0025) covering sidewalls of the second gate structure (120) on the peripheral circuit region (B) of the substrate;
a first capping layer (142b; ¶0025) covering the insulating interlayer (139) on the peripheral circuit region (B) of the substrate;
contact plug structures (180A comprising 181+189; ¶0032) between the bit line structures (140), the contact plug structures (180A) contacting the substrate (impurity regions 15b of substrate 5; Fig. 3A; ¶0032);
first conductive structures (180B; ¶0033) on the first capping layer (142b), a portion of the first conductive structures (185a of 180B) passing through the first capping layer (142b) and the insulating interlayer (139) and contacting the peripheral circuit region of the substrate (via 133; ¶0030; Fig. 3B);
a first upper insulation structure (202b; ¶0039) between the first conductive structures (180B) (Fig. 3B), the first upper insulation structure including a first upper insulation pattern (material of 202b); and
a second upper insulation pattern (202a; ¶0039) between upper portions of the contact plug structures (180A),
wherein at least a portion of the first upper insulation structure (202b) directly contacts the insulating interlayer (139) (as shown in Fig. 3B).
Park is silent regarding wherein the first upper insulation structure (202b) includes a first upper insulation pattern and a hydrogen diffusing insulation pattern surrounding a bottom and sidewalls of the first upper insulation pattern; and
wherein the hydrogen diffusing insulation pattern includes a material having a hydrogen diffusivity higher than a hydrogen diffusivity of silicon nitride, and
wherein at least a portion of the hydrogen diffusing insulation pattern directly contacts the insulating interlayer.
In the same field of endeavor, Kim teaches a similar DRAM device (Fig. 1B; ¶0063) similarly comprising: a second gate structure on a peripheral region (45 of peripheral transistor 40; ¶0024; ¶0041) and upper insulation structure (70p; ¶0045) including a hydrogen diffusing insulation pattern (SiBN layer 71p; ¶0045; this limitation is intended use and therefore the material being the same as what is recited in the specification and claims satisfies this limitation, MPEP 2114) surrounding a bottom and sidewalls of a first upper insulation pattern (72P; ¶0045).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the upper insulation structure of Kim for that of Park in order to achieve good electrical insulation of peripheral interconnections while providing a higher etch resistance (Park; ¶0045, ¶0047, ¶0048). Using Kim’s 70p for Park’s 202b would result in 71p directly contacting the interlayer insulating layer as in Park Fig. 3B.
Regarding Claim 12, modified Park teaches the semiconductor device of claim 11, wherein the hydrogen diffusing insulation pattern includes at least one of silicon oxide, or silicon nitride mixed with other materials as impurities (as modified; 71P is SiBN which is SiN mixed with impurity boron; ¶0045).
Regarding Claim 13, modified Park teaches the semiconductor device of claim 11, wherein the first upper insulation pattern (202b/ Kim 72p) and the second upper insulation pattern (202a / Kim 72c) include silicon nitride (collectively 202; contain SiN; ¶0124; similarly as modified by Kim; 72p; ¶0045, ¶0030).
Regarding Claim 14, modified Park teaches the semiconductor device of claim 11, wherein the insulating interlayer (139) includes silicon oxide (¶0069), and the first capping layer (142b) includes silicon nitride (¶0071).
Regarding Claim 17, modified Park teaches the semiconductor device of claim 11, wherein the first conductive structures (180B which comprises 185) include a contact plug (185a) contacting the substrate (133 of 5) and a conductive line (185b) contacting the contact plug (185a) on the first capping layer (142b) (as shown in Park Fig. 3B).
Regarding Claim 18, modified Park teaches the semiconductor device of claim 17, wherein the first upper insulation structure (modified 202b) is between conductive lines (185b; ¶0034-¶0035), and passes through the first capping layer (142b) (as shown in Fig. 3B).
Regarding Claim 19, modified Park teaches a semiconductor device (Fig. 1, 2, 3A, 3B), comprising:
bit line structures (140; ¶0023) on a cell region (A; ¶0019) of a substrate (5; ¶0018), the bit line structures (140) extending in one direction (III-III’ direction) parallel to an upper surface of the substrate (5);
a gate structure (120; ¶0024) on a peripheral circuit region (B; ¶0019) of the substrate;
contact plug structures (180A comprising 181+189; ¶0032) between the bit line structures (140), the contact plug structures (180A) contacting the substrate (impurity regions 15b of substrate 5; Fig. 3A; ¶0032);
first conductive structures (180B; ¶0033) on the peripheral circuit region (B) of the substrate (5);
a first upper insulation structure (202b; ¶0039) between the first conductive structures (180B) (Fig. 3B); and
a second upper insulation pattern (202a; ¶0039) between upper portions of the contact plug structures (180A), the second upper insulation pattern (202a) having a stacked structure different from a stacked structure of the first upper insulation structure (202b) (as no specific definition in the instant specification is provided for what “a stacked structure” requires, since 592 of Fig. 22 appears to be a single material; Park satisfies this limitation in view of Fig. 19, wherein the “stacked structure” of 202a {commensurate in scope with Applicant’s 592}, has differently shaped/wider “stacked structure” than 202b).
Park is silent regarding wherein the first upper insulation structure (202b) includes a material having a hydrogen diffusivity higher than a hydrogen diffusivity of silicon nitride.
In the same field of endeavor, Kim teaches a similar DRAM device (Fig. 1A; ¶0063) similarly comprising: a second gate structure on a peripheral region (45 of peripheral transistor 40; ¶0024; ¶0041) and second upper insulation structure (70p; ¶0045) including a hydrogen diffusing insulation pattern (SiBN layer 71p; ¶0045; this limitation is intended use and therefore the material being the same as what is recited in the specification and claims satisfies this limitation, MPEP 2114) surrounding a bottom and sidewalls of a first upper insulation pattern (72P; ¶0045), wherein 70p has a stacked structure different from that of a stacked structure of a first insulation structure (70c; ¶0030) formed in a cell region (CA; ¶0025) of the substrate (10; ¶0024) (as shown in Fig. 1A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the above features of Kim for that of Park in order to achieve good electrical insulation of peripheral interconnections while providing a higher etch resistance (Park; ¶0045, ¶0047, ¶0048).
Regarding Claim 20, modified Park teaches the semiconductor device of claim 19, wherein the first upper insulation structure (202b modified to include Kim’s 71p/72p) includes a first upper insulation pattern (72p) including silicon nitride (Kim; ¶0045) and a hydrogen diffusing insulation pattern (this limitation is intended use and therefore the material being the same as what is recited in the specification and claims satisfies this limitation, MPEP 2114; 71p) surrounding a bottom and sidewalls of the first upper insulation pattern (72p as shown in Kim Fig. 1A), and the second upper insulation pattern (202a) includes silicon nitride (Park; ¶0124),
wherein the hydrogen diffusing insulation pattern (71p) includes a material having a hydrogen diffusivity higher than a hydrogen diffusivity of silicon nitride (as 71P includes a same SiBN material as in the instant specification this limitation is satisfied).
Claims 7, 8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Kim in view of Se Ra Hwang (US 20230037646 A1; hereinafter Hwang).
Regarding Claim 7, modified Park teaches the semiconductor device of claim 6, but is silent regarding wherein the etch stop layer (204) includes a material having an etch selectivity with respect to silicon oxide (although ESL 204 is contacting silicon oxide 220) and having a hydrogen diffusivity higher than a hydrogen diffusivity of silicon nitride.
In the same field of endeavor, Hwang teaches a similar semiconductor device (in view of Fig. 1 and Fig. 14) comprising a cell region (CA; ¶0018) and a peripheral region (PA; ¶0018), the peripheral region comprising peripheral transistors (¶0031), wherein an etch stop layer (30; ¶0077) comprising SiBN or SiCN is formed over both regions.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the SiBN or SiCN etch stop layer material of Hwang for the etch stop layer material of Park because of their art-recognized equivalence for the intended use of an etch stop layer over memory device transistors (Hwang; Fig. 14; ¶0077; wherein any suitable material chosen from SiN, SiCN, SiOCN, SiBN, or SiBCN may equivalently serve as the etch stop layer 30 over the memory device transistors, which all have etch selectivity with respect to silicon oxide because they are different materials).
Regarding Claim 8, modified Park teaches the semiconductor device of claim 6, but is silent regarding wherein the etch stop layer (204) includes at least one of SiCN or SiBN.
In the same field of endeavor, Hwang teaches a similar semiconductor device (in view of Fig. 1 and Fig. 14) comprising a cell region (CA; ¶0018) and a peripheral region (PA; ¶0018), the peripheral region comprising peripheral transistors (¶0031), wherein an etch stop layer (30; ¶0077) comprising SiBN or SiCN is formed over both regions.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the SiBN or SiCN etch stop layer material of Hwang for the etch stop layer material of Park because of their art-recognized equivalence for the intended use of an etch stop layer over memory device transistors (Hwang; Fig. 14; ¶0077; wherein any suitable material chosen from SiN, SiCN, SiOCN, SiBN, or SiBCN may equivalently serve as the etch stop layer 30 over the memory device transistors, which all have etch selectivity with respect to silicon oxide because they are different materials).
Regarding Claim 15, modified Park teaches the semiconductor device of claim 11, further comprising:
an etch stop layer (204; ¶0043) on the first conductive structures (180B), the first upper insulation structure (modified 202b), the contact plug structures (180A), and the second upper insulation pattern (202a) (as shown in Park Fig. 3A and 3B), and
a cell capacitor (210; ¶0042) on the cell region (A) of the substrate, the cell capacitor passing through the etch stop layer (204) and contacting the contact plug structures (180A) (as shown in Fig. 3A; ¶0043).
Park is silent regarding wherein the etch stop layer includes a material having a hydrogen diffusivity higher than a hydrogen diffusivity of silicon nitride.
In the same field of endeavor, Hwang teaches a similar semiconductor device (in view of Fig. 1 and Fig. 14) comprising a cell region (CA; ¶0018) and a peripheral region (PA; ¶0018), the peripheral region comprising peripheral transistors (¶0031), wherein an etch stop layer (30; ¶0077) comprising SiBN or SiCN is formed over both regions.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the SiBN or SiCN etch stop layer material of Hwang for the etch stop layer material of Park because of their art-recognized equivalence for the intended use of an etch stop layer over memory device transistors (Hwang; Fig. 14; ¶0077; wherein any suitable material chosen from SiN, SiCN, SiOCN, SiBN, or SiBCN may equivalently serve as the etch stop layer 30 over the memory device transistors, which all have etch selectivity with respect to silicon oxide because they are different materials).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kim, Hwang, and Jin Sub Kim et al. (US 20210375877 A1; hereinafter Kim877).
Regarding Claim 16, modified Park teaches the semiconductor device of claim 15, but is silent regarding further comprising a hydrogen supplying oxide layer on the cell capacitor (210) and the etch stop layer (204).
In the same field of endeavor, Kim877 teaches a similar memory device in Fig. 3; including a cell region (CELL) and peripheral region (PERI; ¶0030), wherein the cell region includes a capacitor (CAP; ¶0046) extending through an etch stop layer (200; ¶0065) to contact device contact structures (105; ¶0059), an interface layer (300 comprising 310 and 320; ¶0096) on the top and side of the capacitor (Fig. 3 and Fig. 5; CAP; and not in the PERI region) wherein a hydrogen supplying oxide layer (400; ¶0115) is disposed on the cell capacitor (CAP) in both the (CELL) and (PERI) regions.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the above features including the hydrogen supplying layer (of Kim877; 400) and interface layer (of Kim877; 300) on the cell capacitor (of Park) in order to prevent hydrogen supply to the capacitor while providing hydrogen to the transistors such that electrical characteristics can be improved (Kim877; ¶0132-¶0135).
Conclusion
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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