Prosecution Insights
Last updated: July 17, 2026
Application No. 18/517,496

FERROELECTRIC MEMORY DEVICE AND MANUFACTURING METHOD OF THE FERROELECTRIC MEMORY DEVICE

Non-Final OA §103§112
Filed
Nov 22, 2023
Priority
Jun 21, 2023 — RE 10-2023-0079539
Examiner
BERRY, PAUL ANTHONY
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
35 granted / 40 resolved
+19.5% vs TC avg
Minimal -4% lift
Without
With
+-3.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
29 currently pending
Career history
90
Total Applications
across all art units

Statute-Specific Performance

§103
92.3%
+52.3% vs TC avg
§102
3.2%
-36.8% vs TC avg
§112
4.5%
-35.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 40 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 9-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II and Device Embodiment 2, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/13/2026. Applicant’s election without traverse of an invention in the reply filed on 03/13/2026 is acknowledged. Claim Objections Claim 1 is objected to because of the following informalities: examiner notes a typographical error. Examiner has interpreted “t he” in the 5th line of the claim as “the”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 7 recites the limitation "the thickness…of the protrusion part" in last two lines of the claim. There is insufficient antecedent basis for this limitation in the claim. Examiner, for purposes of examination, interprets “the thickness…of the protrusion part” as “a thickness…of the protrusion part”. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sakuma et al. (US 2021/0082957 A1, hereinafter Sakuma ‘957) in view of Yoo (US 2018/0358380 A1, hereinafter Yoo ‘380), in view of the following arguments. With respect to Claim 1 Sakuma ‘957 discloses a ferroelectric memory device (Fig 1-11) comprising: a gate stack structure (20, Fig 2A, Para [0055]) including a plurality of interlayer insulating layers (14, Fig 2A, Para [0055]) and a plurality of conductive layers (WL (comprising 11 and 12), Fig 2A, Para [0056]), which are alternately stacked (disclosed in Para [0055] and Fig 2A); a channel layer (10, Fig 2A, Para [0068]) extending in a vertical direction (z direction disclosed in Fig 2A and Para [0066]) (the stacking direction) (10 extending in z direction disclosed in Fig 2A and Para [0066]) in the gate stack structure (20); ferroelectric patterns (16a, Fig 2A, Para [0073]) interposed between (disclosed in Fig 2A) the plurality of conductive layers (WL) and the channel layer (10); and patterns (16b, Fig 2A, Para [0073]) interposed between (disclosed in Fig 2A) the plurality of interlayer insulating layers (14) and the channel layer (10). But Sakuma ‘957 fails to explicitly disclose anti-ferroelectric patterns interposed between the plurality of interlayer insulating layers and the channel layer. Nevertheless, in a related endeavor (Fig 1-15 of Yoo ‘380), Yoo ‘380 teaches anti-ferroelectric patterns (145a, Fig 2B of Yoo ‘380, Para [0041]) interposed between the plurality of interlayer insulating layers (110a-110f, Fig 2B of Yoo ‘380, Para [0036]) and the channel layer (175, Fig 2B of Yoo ‘380, Para [0030]). Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yoo ‘380’s teaching of anti-ferroelectric patterns interposed between the plurality of interlayer insulating layers and the channel layer into Sakuma ‘957’s device. Sakuma ‘957 discloses a ferroelectric non-volatile memory structure with stacked conductive word lines and insulative layers and ferroelectric patterns and paraelectric regions between the conductive and insulating layers, respectfully, and the channel layer. Yoo ‘380 teaches a ferroelectric non-volatile memory structure with stacked conductive word lines and insulative layers and teaches (Para [0041] of Yoo ‘380) that anti-ferroelectric patterns can be used, in place of the paraelectric material between the insulative layers and the channel layer. Therefore a person of ordinary skill in the art would have a reasonable expectation of success in using the anti-ferroelectric material taught by Yoo ‘380 instead of the paraelectric material taught by Sakuma ‘957. Further one of ordinary skill in the art would recognize that both paraelectric and anti-ferroelectric materials provide the well-known advantage of providing an insulating material property in a ferro-electric memory device. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings Sakuma ‘957 with Yoo ‘380 to obtain the invention as specified in claim 1. And the ordinary artisan would have been motivated to modify Sakuma ‘957 in the manner set forth above, at least, because the anti-ferroelectric materials of Yoo ‘380 have zero net polarization at zero field, and can switch to a polar state under an electric field. As incorporated, the anti-ferroelectric patterns (145a) taught by Yoo ‘380 would be used instead of the paraelectric patterns (16b) of Sakuma ‘957 in the device of Sakuma ‘957. With respect to Claim 2 Sakuma ‘957 as modified by Yoo ‘380 discloses all limitations of the ferroelectric memory device of claim 1, and Sakuma ‘957 as modified by Yoo ‘380 further discloses wherein the ferroelectric patterns (16a) and the anti-ferroelectric patterns (145a of Yoo ‘380 as incorporated into Sakuma ‘957 as described above) include the same material (Para [0071] of Sakuma ‘957 discloses layer 16 (of which 16a is a part of) contains hafnium oxide and Para [0039] of Yoo ‘380 discloses 145a comprises hafnium oxide). And Yoo ‘380 further teaches wherein the ferroelectric patterns include oxygen vacancies. (Para [0040] of Yoo ‘380 teaches ferroelectric pattern 155 of Yoo ‘380 include oxygen vacancies and the anti-ferroelectric pattern 145a also has oxygen vacancies). Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yoo ‘380’s further teaching of the ferroelectric patterns include oxygen vacancies into Sakuma ‘957 as modified by Yoo ‘380’s device. Sakuma ‘957 as modified by Yoo ‘380 discloses a ferroelectric non-volatile memory structure with stacked conductive word lines and insulative layers and ferroelectric patterns and anti-ferroelectric regions between the conductive and insulating layers. And Yoo ‘380 further teaches the use of oxygen vacancies in a same material of the ferroelectric and anti-ferroelectric material. Therefore, the ordinary artisan would have been motivated to modify Sakuma ‘957 in the manner set forth above, at least, because as Yoo ‘380 teaches in Para [0058-0059] creating oxygen vacancies in the ferroelectric and anti-ferroelectric materials enables a tensile or compressive strain between the ferroelectric and antiferroelectric materials which can improve the performance of the ferroelectric material and it can also enable an electric field to be created between the ferroelectric and anti-ferroelectric materials which also can enable the ferroelectric material to exhibit a relatively strong ferroelectric property. As incorporated, the teachings of Yoo ‘380 of having oxygen vacancies in the ferroelectric and anti-ferroelectric materials would be used in the ferroelectric material (16a) of Sakuma ‘957 and the anti-ferroelectric material (145a of Yoo ‘380 as incorporated into Sakuma ‘957) in the device of Sakuma ‘957 as modified by Yoo ‘380. With respect to Claim 3 Sakuma ‘957 as modified by Yoo ‘380 discloses all limitations of the ferroelectric memory device of claim 1, and Yoo ‘380 further discloses wherein each of the anti-ferroelectric patterns (145a of Yoo ‘380 as incorporated into Sakuma ‘957) is interposed between (Fig 2A discloses 16b (which as described above is the location of 145a of Yoo ‘380 as incorporated into Sakuma ‘957) interposed between 16a) the ferroelectric patterns (16a) adjacent to each other in the vertical direction (Fig 2A discloses 16a and 16b (which as described above is the location of 145a of Yoo ‘380 as incorporated into Sakuma ‘957) adjacent to each other in the z direction). PNG media_image1.png 536 887 media_image1.png Greyscale With respect to Claim 4 Sakuma ‘957 as modified by Yoo ‘380 discloses all limitations of the ferroelectric memory device of claim 1, and Sakuma ‘957 further discloses including a blocking layer (blocking layer (portion of hafnium oxide 16b above word line extension) as shown in annotated Fig 2A of Shakuma ‘957, Para [0077]) interposed between (blocking layer interposed between 14 and 16b ( disclosed in Fig 2A) the plurality of interlayer insulating layers (14) and the anti-ferroelectric patterns (145a, (Fig 2A discloses area of 16b to right of blocking layer (which as described above is the location of 145a of Yoo ‘380 as incorporated into Sakuma ‘957). PNG media_image2.png 527 788 media_image2.png Greyscale With respect to Claim 5 Sakuma ‘957 as modified by Yoo ‘380 discloses all limitations of the ferroelectric memory device of claim 1, and Sakuma ‘957 discloses further wherein each of the plurality of conductive layers (WL) includes a protrusion part (protrusion part denoted in annotated Fig 2A_1 of Sakuma ‘957) protruding farther toward the channel layer (10) than the plurality of interlayer insulating layers (14)(annotated Fig 2A_1 of Sakuma ‘957 discloses protrusion part protruding farther toward channel layer than insulating layers). With respect to Claim 7 Sakuma ‘957 as modified by Yoo ‘380 discloses all limitations of the ferroelectric memory device of claim 5, but Sakuma ‘957 as modified by Yoo ‘380 further discloses wherein a thickness (a thickness of 16a shown in annotated Fig 2A_1 of Sakuma ‘957) in the vertical direction (z direction) of each of the ferroelectric patterns (16a) is thinner than the thickness (note Examiner, for purposes of examination, interprets “the thickness…of the protrusion part” as “a thickness…of the protrusion part”) (thickness of protrusion part shown in annotated Fig 2A_1 of Sakuma ‘957) in the vertical direction (z direction) of the protrusion part (protrusion part denoted in annotated Fig 2A_1 of Sakuma ‘957)(claim does not cite reference points for thickness, therefore a thickness of the ferroelectric patterns (16a) exists that is thinner than a thickness of the protrusion part as shown in annotated Fig 2A_1 of Sakuma ‘957). Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Sakuma ‘957 in view of Yoo ‘380 in further view of Mukae et al. (US 2022/0352199 A1, hereinafter Mukae ‘199) in view of the following arguments. PNG media_image3.png 511 771 media_image3.png Greyscale With respect to Claim 6 Sakuma ‘957 as modified by Yoo ‘380 discloses all limitations of the ferroelectric memory device of claim 5, but Sakuma ‘957 as modified by Yoo ‘380 fails to explicitly disclose wherein a thickness of the protrusion part of each of the plurality of conductive layers is thicker in the vertical direction than a thickness in the vertical direction of the other part of each of the plurality of conductive layers interposed between the plurality of interlayer insulating layers. Nevertheless, in a related endeavor (Fig 64A-66B of Mukae ‘199), Mukae ‘199 teaches a thickness of the protrusion part (protrusion part of 46 as shown in Fig 66B of Mukae ‘199, Para [0314]) of each of the plurality of conductive layers (46, Fig 66B of Mukae ‘199, Para [0314]) is thicker in the vertical direction (vertical direction shown in annotated Fig 66B of Mukae ‘199) than a thickness in the vertical direction of the other part (other part of 46 shown in annotated Fig 66B of Mukae ‘199) of each of the plurality of conductive layers (46) interposed between the plurality of interlayer insulating layers (32, Fig 66B of Mukae ‘199, Para [0318])(annotated Fig 66B of Mukae ‘199 discloses thickness of protrusion area thicker than the other part of 45 in the vertical direction). Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Mukae ‘199’s teaching of a thickness of the protrusion part of each of the plurality of conductive layers is thicker in the vertical direction than a thickness in the vertical direction of the other part of each of the plurality of conductive layers interposed between the plurality of interlayer insulating layers into Sakuma ‘957 as modified by Yoo ‘380’s device. Sakuma ‘957 as modified by Yoo ‘380 discloses a ferroelectric non-volatile memory structure with stacked conductive word lines and insulative layers and ferroelectric patterns and paraelectric regions between the conductive and insulating layers, respectfully, and the channel layer, wherein the conductive layer protrudes farther to the channel layer than the insulative layer. Mukae ‘199 teaches a non-volatile memory structure with stacked conductive word lines and insulative layers, a channel layer and wherein the conductive layer protrudes farther to the channel layer than the insulative layer and also teaches the protrusion thickness is greater than the rest of the conductive layer. Therefore a person of ordinary skill in the art would have a reasonable expectation of success as incorporating the design of the protruding conductive feature of Mukae ‘199 in the device of Sakuma ‘957 as modified by Yoo ‘380 they are both word lines in a non-volatile memory device. Further the ordinary artisan would have been motivated to modify Sakuma ‘957 as modified by Yoo ‘380 in the manner set forth above, at least, as Mukae ‘199 teaches (Para [0314] of Mukae ‘199) that the protruding portion of the conductive layer having a greater thickness than the rest of the conductive layer suppresses a short channel effect without increasing the word line and gate electrode capacitance. As incorporated, the protruding part of the conductive layer having a greater thickness than the rest of the conductive layer as taught by Mukae ‘199 would be used as the shape of the protruding part (shown in annotated Fig 2A_1 of Sakuma ‘957) of the conductive layer (WL) of Sakuma ‘957 as modified by Yoo ‘380. With respect to Claim 8 Sakuma ‘957 as modified by Yoo ‘380 discloses all limitations of the ferroelectric memory device of claim 1, but Sakuma ‘957 as modified by Yoo ‘380 fails to explicitly disclose wherein an end portion of each of the plurality of conductive layers in a direction toward the channel layer has a “T” shape. Nevertheless, in a related endeavor (Fig 64A-66B of Mukae ‘199), Mukae ‘199 teaches an end portion (end portion, protrusion part of 46 as shown in Fig 66B of Mukae ‘199, Para [0314]) of each of the plurality of conductive layers (46, Fig 66B of Mukae ‘199, Para [0314]) in a direction toward (horizontal direction as show in annotated Fig 66B of Mukae ‘199) the channel layer has a “T” shape (Fig 66B of Mukae ‘199 and Para [0314] disclose the end portion of the conductive layer has a “T” shape). Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Mukae ‘199’s teaching of an end portion of each of the plurality of conductive layers in a direction toward the channel layer has a “T” shape into Sakuma ‘957 as modified by Yoo ‘380’s device. Sakuma ‘957 as modified by Yoo ‘380 discloses a ferroelectric non-volatile memory structure with stacked conductive word lines and insulative layers and ferroelectric patterns and paraelectric regions between the conductive and insulating layers, respectfully, and the channel layer, wherein the conductive layer protrudes farther to the channel layer than the insulative layer. Mukae ‘199 teaches a non-volatile memory structure with stacked conductive word lines and insulative layers, a channel layer and wherein the conductive layer protrudes farther to the channel layer than the insulative layer and also teaches the protrusion thickness is greater than the rest of the conductive layer. Therefore a person of ordinary skill in the art would have a reasonable expectation of success as incorporating the design of the protruding conductive feature of Mukae ‘199 in the device of Sakuma ‘957 as modified by Yoo ‘380 they are both word lines in a non-volatile memory device. Further the ordinary artisan would have been motivated to modify Sakuma ‘957 as modified by Yoo ‘380 in the manner set forth above, at least, as Mukae ‘199 teaches (Para [0314] of Mukae ‘199) that the protruding portion of the conductive layer having a “T” shape suppresses a short channel effect without increasing the word line and gate electrode capacitance. As incorporated, the end portion of each of the plurality of conductive layers in a direction toward the channel layer having a “T” shape as taught by Mukae ‘199 would be used as the shape of the protruding part (shown in annotated Fig 2A_1 of Sakuma ‘957) of the conductive layer (WL) of Sakuma ‘957 as modified by Yoo ‘380. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Nov 22, 2023
Application Filed
May 21, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
84%
With Interview (-3.8%)
3y 4m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 40 resolved cases by this examiner. Grant probability derived from career allowance rate.

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