DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/18/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US Pub. 2021/0118500) in view of Kim et al. (US Pub. 2020/0143871).
Regarding claims 1 and 7, Fig. 7 of Shin discloses a method for refreshing a flash memory device, wherein the flash memory device comprises a main control unit [110, Fig. 4] and a plurality of flash memory units [within Memory Device 200, Fig. 4], the method comprising steps of:
sending a performance value related to the plurality of flash memory units from the main control unit to a host [as discloses in paragraph 0100, when one of the memory unit fails to pass the sensing, the sensing data is transmitted to the host];
sending a refresh command from the host to the main control unit when the performance value is lower than a pre-determined value [as discloses in paragraph, when memory fails sensing operation (equivalent to performance less than a pre-determined value), host send commands to memory device to start refreshing operation, see paragraph 0045]; and
enabling the main control unit to stop current operations of the plurality of flash memory units and execute a refresh operation on all valid data blocks [valid data block is relative. A data block can be valid to one user/controller and might not be valid for other. In this instances, all data on the memory block that the controller performing refreshing operation are valid data. Applicant need to clearly define what is valid data and what is not valid data] of the plurality of flash memory units in the flash memory device [as discloses in paragraph 0040, when refresh operation is executed, other memory operations are stopped. In addition, as shows in Fig. 7, when refresh operation (S140) performs, no other memory operation occurs at the same time].
Paragraph 0043 of Shin discloses user can control/activate various operations of the memory device. Since Shin operates refreshing operation, it is obvious if not inherent that Shin memory device user to send command to activate refreshing operation. In addition, Fig. 1 of Kim discloses a memory device [200] connects to a host [100], wherein user can input refresh command to a host [100] so that the host can send refresh command to memory controller to start refreshing operation [paragraphs 0040 and 0069].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kim’s memory device having memory controller connects to a host to the teachings of Shin’s memory having memory controller and host such that Shin memory device operate in response to user command according to Kim’s teachings for the purpose of allowing user to control the memory operations.
Regarding claim 2, Fig. 7 of Shin discloses prior to the step of sending the performance value from the main control unit, the method further comprising a step of: sending a request [as shows in Fig. 7, before data send to host in step S130, the host send command to start a read operation. By sending a reading command, the host indirectly initiate the transfer of data to the host if the reading fails] of the performance value related to the plurality of flash memory units from the host [100, Fig. 4] to the main control unit [110, Fig. 4].
Regarding claims 3, 8, Fig. 12 of Shin discloses after the main control unit executes the refresh operation [step S142], the method further comprising a step of: sending a refresh status from the main control unit to the host [S144] to show whether each of the plurality of flash memory units has been refreshed.
Regarding claims 4, 9, and 14, Fig 5 of Shin discloses wherein the refresh command conforms to the requirements of non-volatile memory express (NVMe), serial advanced technologyattachment (SATA), inter-integrated circuit (12C) bus or general-purpose input/output (GPIO) [paragraphs 0046 to 0052].
Regarding claims 5, 10, Fig. 4 of Shin discloses wherein: the main control unit [110] is electrically connected to the host [100]; and the plurality of flash memory units [200] are electrically connected to the main control unit [110].
Regarding claims 6, 11, 13, Fig. 5 of Shin discloses wherein the main control unit comprises: a processing unit [220] configured to electrically communicate with the host [100, Fig. 4] through an interface unit [300]; a control logic unit [221] electrically connected between the processing unit and the plurality of flash memory units [210] and configured to be controlled by the processing unit to control the refresh operation on the plurality of flash memory units; and a buffer management unit [216] electrically connected between the control logic unit and the processing unit and configured to temporarily store data originally stored in the plurality of flash memory units during the refresh operation.
Regarding claim 12, Fig. 4 of Shin discloses a system for refreshing a flash memory device, the system comprising:
a host [100];
a main control unit [110, or 220 in Fig. 5] disposed in the flash memory device [200] and connected to the host [100]; and
a plurality of flash memory units [210, Fig. 5] disposed in the flash memory device [200] and connected to the main control unit [220, Fig. 5],
wherein the host [100] is configured to send a refresh command to the main control unit [paragraph 0045] to enable the main control unit to stop current operations of the plurality of flash memory units and execute a refresh operation on all valid data blocks [valid data block is relative. A data block can be valid to one user/controller and might not be valid for other. In this instances, all data on the memory block that the controller performing refreshing operation are valid data. Applicant need to clearly define what is valid data and what is not valid data] of the plurality of flash memory units in the flash memory device [as discloses in paragraph 0040, when refresh operation is executed, other memory operations are stopped. In addition, as shows in Fig. 7, when refresh operation (S140) performs, no other memory operation occurs at the same time].
Paragraph 0043 of Shin discloses user can control/activate various operations of the memory device. Since Shin operates refreshing operation, it is obvious if not inherent that Shin memory device user to send command to activate refreshing operation. In addition, Fig. 1 of Kim discloses a memory device [200] connects to a host [100], an interface disposed on the host [since user can input command through host 100, an interface disposed on the host is inherent], wherein user can input refresh command to a host [100] so that the host can send refresh command to memory controller to start refreshing operation [paragraphs 0040 and 0069].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kim’s memory device having memory controller connects to a host to the teachings of Shin’s memory having memory controller and host such that Shin memory device operate in response to user command according to Kim’s teachings for the purpose of allowing user to control the memory operations.
Response to Arguments
Applicant's arguments filed 11/18/2025 have been fully considered but they are not persuasive. Applicant argues that Shin does not teach or suggest the host sending refreshing command to execute refresh operation on all valid data blocks of the plurality of flash memory units in the flash memory device. Applicant is reminded that the claims are examined in light of broadest reasonable interpretation. In addition, although the claims are examined in light of specification, limitations from specification are not read into the claims. “Valid data block” is relative. A data block can be valid to one user/controller and might not be valid for other. Since applicant does not clearly define what is and what is not valid data, any data stores in the refreshing memory cells are considered valid data. Therefore, all the data stores in the memory blocks that are being refreshing are considered all valid data block. Applicant need to clearly define what is valid data and what is not valid data. In addition, paragraph 0067 of Redaelli (US Pub. 2024/0069768) teach refreshing all memory blocks.
Therefore, all applicant arguments were fully considered, they are not persuasive.
Conclusion
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825