Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1 – 13 and 15 – 20 in the reply filed on 06/09/2026 is acknowledged.
Claim 14 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/09/2026.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 11/22/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract of the disclosure is objected to because the abstract contains information already present in the title. Specifically, the abstract states “A semiconductor package is provided. The semiconductor package includes a…”. The title already states “SEMICONDUCTOR PACKAGE”. The abstract should be corrected to remove the title information from the abstract. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
Claims 3 – 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “about” in claims 3 and 8 is a relative term which renders the claims indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Regarding claims 3 and 8, it is unclear what “about” means in regard to how close the distance between stacked vias have to be to 38 nm and how much that distance can deviate away form 38 nm. It is unclear if “about” means 5% deviation or 10% deviation, or a deviation from 38 nm that could result in ranges from 38 – 50 nm or 38 – 38.5 nm.
Claims 4 – 7 depend on claim 3 and inherit all of its deficiencies. Claims 4 – 7 are rejected as being indefinite.
For the purpose of compact prosecution, examiner is interpreting claim 3 as meaning “…a horizontal distance between any two of the plurality of lower stacked vias is less than 38 nm” and claim 8 as stating “…a horizontal distance between two of the plurality of lower non-stacked vias is greater than 38 nm”. These interpretations appear consistent with the specification and removes the indefinite language from the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 2, 13, and 15 - 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220319957 A1 hereinafter Hsiao in further view of US 20200176397 A1 hereinafter Liu.
For claim 1, Hsiao teaches a semiconductor package (Hsiao, fig. 8) comprising: a semiconductor substrate (fig. 8 numeral 60); a lower interconnect structure formed over the semiconductor substrate (fig. 8 numeral 68), wherein the lower interconnect structure comprises a plurality of lower dielectric layers (fig. 8 numeral 72, 74, 76) and a plurality of lower metal lines (fig. 8 numeral L1, L2, L3) and a plurality of metal vias formed in the plurality of lower dielectric layers (fig. 8 numeral V2, V3); an upper interconnect structure formed over the lower interconnect structure (fig. 8 numeral 130): a conductive pad over the upper interconnect structure (fig. 8 numeral 132); and a pillar bump structure in direct contact with the conductive pad (fig. 8 numeral 134). Hsiao is silent regarding the pillar bump structure comprises at least two protrusions that protrude towards the conductive pad and are laterally separated from each other.
Liu teaches an interconnect structure (Liu, fig. 15 numeral 122) including dielectric layers (fig. 15 numeral 124, 128, 132) and metal lines with vias (fig. 15 numeral 130, 134). A pillar bump is provided on the interconnect structure (fig. 15 numeral 138), and the pillar bump comprises two protrusions that protrude towards the interconnect structure (fig. 15 numeral 138A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the two protrusions in Liu with the pillar bump in Hsiao in order to improve mechanical reliability of the pillar bump structure and improve thermal stress resistance (Liu, Par. [0049]).
For claim 2, Hsiao and Liu teach all of claim 1. Hsiao and Liu do not explicitly state that the ratio of areas of the two protrusions to an area of the pillar bump in a bottom view is in a range of 0.10 to 0.75. However, Liu does teach that the widths of the pillar bump structure may be 2.5 to 3.6 times greater than the width of the protrusions (Liu, Par. [0048]). Liu also teaches that both the pillar bump structure and the protrusions may have a circle shape in a bottom view (Liu, fig. 17A shows a top-down view including both the protrusions 138A and the pillar bump 138B, inverting this view gives a bottom view with the same shapes). As both shapes are circular in a bottom view, the areas of the protrusions and the pillar bump structure are A = πr2 and the ratio of the areas would simplify to the radius of the protrusions divided by the radius of the pillar bump structure.
The radius of the protrusions would be (W1)/2 in figure 15, combining the radiuses gives (W1+W1)/2. The radius of the pillar bump structure would be (W2)/2. Simplifying the ratio gives (W1+W1)/(W2). Paragraph [0048] in Liu includes the ratio between W2 and W1 is 2.5 to 3.6. With the first width W1 being set to 1 and the second width W2 is at the upper bound of 3.6 the ratio of the two areas becomes (1 + 1)/(3.6) which is equal to about .56. This gives the ratio of areas of the at least two protrusions to an area of the pillar bump structure that is between 0.10 and 0.75 in Liu. Similarly, numbers given in Liu include W2 being at least 50 µm. If W2 is 3.6 times greater than W1 as taught in Liu (Par. [0048]), W1 would have to be approximately 14 µm. The same ratio equation gives (14 + 14)/50 which is approximately .56, and is an area ratio of between 0.10 and 0.75.
For claim 13, Hsiao teaches a semiconductor package (Hsiao, fig. 8) comprising: a semiconductor substrate (fig. 8 numeral 60); a lower interconnect structure formed over the semiconductor substrate (fig. 8 numeral 68), wherein the lower interconnect structure comprises a plurality of lower dielectric layers (fig. 8 numeral 72, 74, 76) and a plurality of lower metal lines (fig. 8 numeral L1, L2, L3) and a plurality of metal vias formed in the plurality of lower dielectric layers (fig. 8 numeral V2, V3); an upper interconnect structure formed over the lower interconnect structure (fig. 8 numeral 130), wherein the upper interconnect structure comprises a plurality of upper dielectric layers (fig. 8 numeral 122) and a plurality of upper metal vias formed in the plurality of upper dielectric layers (fig. 8 numeral 126), a conductive pad over the upper interconnect structure and electrically connected to the plurality of upper metal vias (fig. 8 numeral 132); and a pillar bump structure in direct contact with the top surface of the conductive pad (fig. 8 numeral 134). Hsiao also teaches the upper dielectric layers comprises a material that is different from a material of the plurality of lower dielectric layers (Par. [0035]; Par. [0012 - 0015]).
Hsiao is silent regarding the pillar bump structure comprises a first protrusion and a second protrusion that are spaced apart from each other.
Liu teaches an interconnect structure (Liu, fig. 15 numeral 122) including dielectric layers (fig. 15 numeral 124, 128, 132) and metal lines with vias (fig. 15 numeral 130, 134). A pillar bump is provided on the interconnect structure (fig. 15 numeral 138), and the pillar bump comprises two protrusions that protrude towards the interconnect structure and the protrusions are spaced apart from each other (fig. 15 numeral 138A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the two protrusions in Liu with the pillar bump in Hsiao in order to improve mechanical reliability of the pillar bump structure and improve thermal stress resistance (Liu, Par. [0049]).
For claim 15, Hsiao and Liu teach all of claim 13. Hsiao and Liu do not explicitly state that from a bottom view, a first area of the first protrusion is different from a second are of the second protrusion. However, Liu does teach embodiments wherein the widths of the two protrusions are different from each other (Liu, fig. 16 numeral W1C and W1D), and that the protrusions can be various shapes including circular shapes from a bottom view (fig. 17A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the areas of the first protrusion and the second protrusions in Liu would be different as the widths of the two protrusions are taught to be variable and different between the two protrusions, and that a circular shape of the protrusions would result in the difference widths resulting in different radius for each protrusion, and would result in different areas for each protrusion. Liu also teaches that each protrusion may be a different shape, which would result in different areas depending on which shape each protrusion has (Par. [0053]).
For claim 16, Hsiao and Liu teach all of claim 13. Liu also teaches that the protrusions can be different shapes (Liu, fig. 17A – 17O) and that the protrusions can be different shapes on the same package (Par. [0053]).
Claim(s) 18 – 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20220319957 A1 hereinafter Hsiao in view of US 20200176397 A1 hereinafter Liu and in further view of US 20140225258 A1 hereinafter Chiu.
For claim 18, Hsiao teaches a an interconnect structure comprising: an interconnect structure comprising a plurality of dielectric layers (Hsiao, fig. 8 numeral 72, 74, 76) and a plurality of metal lines (fig. 8 numeral L1, L2, L3) and a plurality of stacked vias formed in the plurality of dielectric layers (fig. 8 numeral V2, V3), a pillar bump structure formed on the interconnect structure (fig. 8 numeral 134), and one of the pillar bumps is shown to be offset from the stacked via creating a projection area spaced apart from the projection area of the stacked vias (fig. 8, the pillar pump 134 includes at least two pillar bumps on the right side of the device that do not overlap the stacked vias V2 and V3). Hsiao is silent regarding a first passivation layer over the interconnect structure; a second passivation layer formed over the first passivation layer; and a polymeric layer formed over the second passivation layer. Hsiao is also silent regarding the pillar bump structure including a first protrusion extending into the polymeric layer.
Liu teaches an interconnect structure comprising dielectric layers (fig. 15 numeral 124, 128, 132) and metal lines with vias (fig. 15 numeral 134, 130), and a polymeric layer formed over the interconnect structure (fig. 15 numeral 136; Par. [0033]; Par. [0039]). Liu also teaches a pillar bump (fig. 15 numeral 138) with a protrusion that extends into the polymeric layer (fig. 15 numeral 138A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the protrusions in Liu with the pillar bump in Hsiao in order to improve mechanical reliability of the pillar bump structure and improve thermal stress resistance (Liu, Par. [0049]). Hsiao and Liu are silent regarding a first passivation layer and a second passivation layer over the interconnect structure.
Chiu teaches an interconnect structure (Chiu, fig. 2A) including a first passivation layer over the interconnect structure (fig. 2A numeral 41) and a second passivation layer over the first passivation layer (fig. 2A numeral 42), and the passivation layers are between the interconnect structure and a pillar bump (fig. 2A numeral 50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the multiple passivation layers in Chiu with the interconnect structure and protrusions in Liu and Hsiao in order to further isolate the interconnect structure from the outside environment and protect the interconnect structure from exposure to moisture or dust.
For claim 19, Hsiao, Liu, and Chiu teach all of claim 18. Liu also teaches the pillar bump structure including a second protrusion (Liu, fig. 15 numeral 138A) that extends into the polymeric layer (fig. 15 numeral 136), and wherein a portion of the polymeric layer is laterally sandwiched between the first protrusion and the second protrusion (fig. 15 shown by thickness T1).
For claim 20, Hsiao, Liu, and Chiu teach all of claim 19. Liu also teaches that a second protrusion (Liu, fig. 15 numeral 138A) is shown to be offset from the stacked vias 134 and 130 in figure 15 of Liu. Hsiao also teaches one of the pillar bumps is shown to be offset from the stacked via creating a projection area spaced apart from the projection area of the stacked vias (Hsiao fig. 8, the pillar pump 134 includes at least two pillar bumps on the right side of the device that do not overlap the stacked vias V2 and V3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the pillar bump structure in Hsiao, Liu, and Chiu would include protrusions that have projected areas offset from the projection areas of the plurality of stacked vias, as Hsiao, Liu, and Chiu teach the location of the pillar bump being variable, and that the location of the pillar bump and the protrusions can be located offset form the stacked vias located below the pillar bump structure.
Allowable Subject Matter
Claims 9 – 12 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For claim 9, Hsiao, Liu, and Chiu do teach the pillar bump structure making direct contact with the conductive pad. However, Hsiao, Liu, and Chiu do not appear to teach the formation of a passivation layer that has a passivation via that allows for the direct contact between the pillar bump structure and the conductive pad. Chiu teaches a plurality of passivation layers being formed (Chiu, fig. 2C numeral 41 and 42) with a passivation via (fig. 2C numeral 46) but an intermediate layer is provided between the pillar bump structure and the conductive pad below the passivation layers, and no direct contact is made between the pillar bump structure and the conductive pad through the passivation via.
Claims 10 – 12 are allowable primarily as being dependent on an allowable base claim.
For claim 17, Hsiao, Liu, and Chiu teach multiple stacked vias and a pillar bump structure with at least two protrusions. Hsiao, Liu, and Chiu do not appear to teach the lower stacked vias being located between the first protrusion and the second protrusion. Liu appears to teach the stacked vias being located on the outside of the first and second protrusions of the pillar bump structure (Liu, fig. 15) and the vias do not appear in the space between the first and second protrusions.
Claims 3 - 8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
For claim 3, Hsiao, Liu, and Chiu do not appear to teach the plurality of lower stacked vias in the lower dielectric layers are separated horizontally from each other by less than 38 nm. Hsiao does teach separating the vias from other metal lines and vias (Hsiao, fig. 7B numeral D1) but the distance provided is .2 to 5 µm which is at least 200 nm, and does not state that the distance is the total distance between stacked vias, only a required distance and further distance between the stacked vias could be possible. It would not be obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to further shrink the distance provided in Hsiao, as the minimum distance provided appears essential to the functioning of the vias.
Claims 4 – 7 would be allowable primarily as depending on claim 3, but are rejected under 35 U.S.C. 112(b) as inheriting the deficiencies of claim 3.
For claim 8, Hsiao does teach separating the vias from other metal lines and vias (Hsiao, fig. 7B numeral D1) and the distance provided is .2 to 5 µm which is at least 200 nm. However, Hsiao appears to teach that the lower vias comprise only stacked vias (fig. 8 numeral V2 and V3) and stacked through vias (fig. 8 numeral 102, 104, 106). Hsiao is silent regarding the distance between each stacked via or if the stacked vias may be non-stacked vias. It would not be obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to change the stacked vias in Hsiao to non-stacked vias, as the lower stacked vias appear to be integral to the functioning of the device in Hsiao.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20200035631 A1 teaches a pillar bump structure with multiple protrusions. It does not appear to teach the lower stacked vias being located between the first protrusion and the second protrusion or that a passivation layer that has a passivation via that allows for the direct contact between the pillar bump structure and the conductive pad.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB T NELSON whose telephone number is (571)272-1031. The examiner can normally be reached Monday through Friday 9:00 AM to 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.T.N./Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
Prosecution Insights