DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/22/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. US 2022/0139921.
Re claim 1, Kim teaches a semiconductor memory device (fig2A) comprising:
a substrate (101, fig2A, [20]) including a plurality of active regions (ACT, fig2A, [20]) in a memory cell region (fig2A);
a plurality of bit line structures (BLS, fig 1 and 2A, [20]) extending in parallel with each other in a first horizontal direction (Y, fig1) in the memory cell region;
a plurality of buried contacts (160 and 165, fig2A, [21]) respectively and electrically connected to the plurality of active regions (ACT, fig2A, [20]), the plurality of buried contacts (160 and 165, fig2A, [21]) partially filling a space between the plurality of bit line structures (BLS, fig 1 and 2A, [20]);
a plurality of lower landing pads (LP1, fig2A, [21]) in the space between the plurality of bit line structures (BLS, fig 1 and 2A, [20]) and respectively on the plurality of buried contacts (160 and 165, fig2A, [21]);
a landing pad insulating structure (180, fig2A, [20]) in contact with the plurality of bit line structures (BLS, fig 1 and 2A, [20]) and the plurality of lower landing pads (LP1, fig2A, [21]), the landing pad insulating structure (180, fig2A, [20]) including a plurality of landing pad holes (space holding LP2, fig2A, [21]);
a plurality of upper landing pads (LP2, fig2A, [21]) respectively filling the plurality of landing pad holes and respectively connected to the plurality of lower landing pads (LP1, fig2A, [21]); and
a plurality of capacitor structures (CAP, fig2A, [20]) including a plurality of lower electrodes (192, fig2A, [62]) respectively and electrically connected to the plurality of upper landing pads (LP2, fig2A, [21]), an upper electrode (196, fig2A, [62]), and a capacitor dielectric layer (194, fig2A, [62]) between the plurality of lower electrodes (192, fig2A, [62]) and the upper electrode (196, fig2A, [62]).
Re claim 2, Kim teaches the semiconductor memory device of claim 1, wherein the landing pad insulating structure (180, fig2A, [20]) includes a plurality of insulating grooves in a lower portion thereof (recess part of lower 180, fig2A), the plurality of insulating grooves being respectively filled with the plurality of bit line structures (BLS, fig 1 and 2A, [20]).
Re claim 3, Kim teaches the semiconductor memory device of claim 2, wherein each of the plurality of bit line structures (BLS, fig 1 and 2A, [20]) includes a cut part in an upper portion thereof (top part of BC covered by LP2, fig2A, [39]), the cut part not being covered with the landing pad insulating structure (180, fig2A, [20]).
Re claim 4, Kim teaches the semiconductor memory device of claim 3, wherein the cut part of each of the plurality of bit line structures has an oblique shape with a slope (top part of BC covered by LP2, fig2A, [39]), and another upper portion of each of the plurality of bit line structures fills one of the plurality of insulating grooves and has a round shape (top part of BC covered by 180, fig1 and 2A, [39]).
Re claim 5, Kim teaches the semiconductor memory device of claim 1, wherein each of the plurality of bit line structures (BLS, fig 1 and 6B, [20]) includes a bit line (141 of BL, fig6B, [54]), an insulating capping line (BC, fig6B, [56]) covering the bit line (141 of BL, fig6B, [54]), and a pair of insulating spacer structures (SS, fig6B, [58]) respectively covering opposite side walls of each of the bit line (141 of BL, fig6B, [54]) and the insulating capping line (BC, fig6B, [56]), a top surface (top surface of LP1 in contact with 180, fig6B, [21]) of each of the plurality of lower landing pads is at a lower vertical level than a topmost surface of each of the plurality of bit line structures (top surface of BC, fig6B, [56]), and a bottom surface (bottom surface of LP1 in contact with 165, fig6B, [21]) of each of the plurality of lower landing pads is at a higher vertical level than a top surface of the bit line (top surface of 141, fig6B, [54]) of each of the plurality of bit line structures.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2022/0139921 in view of Park US 2014/0327063.
Re claim 6, Kim does not explicitly show the semiconductor memory device of claim 1, further comprising: a gate line on the substrate in a peripheral region; a peripheral bit line insulating structure on the gate line, the peripheral bit line insulating structure including a plurality of peripheral bit line recesses and including the same material as the landing pad insulating structure; and a plurality of peripheral bit lines including the same material as the plurality of upper landing pads and respectively filling the plurality of peripheral bit line recesses, wherein the substrate further includes the peripheral region having a peripheral active region therein.
Park teaches a gate line (240, fig16E, [103]) on the substrate in a peripheral region (fig16E); a peripheral bit line insulating structure (180P, fig16E, [122]) on the gate line, the peripheral bit line insulating structure (180P, fig16E, [122]) including a plurality of peripheral bit line recesses (space holding 290P, fig16E, [137]) and including the same material as the landing pad insulating structure (180, fig23A, [135]); and a plurality of peripheral bit lines (290P, fig16E, [137]) including the same material as the plurality of upper landing pads (190L, fig23A, [136]) and respectively filling the plurality of peripheral bit line recesses, wherein the substrate further includes the peripheral region having a peripheral active region therein (116, fig16E, [84]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kim and Park to form the Peripheral circuit region together with the core region. The motivation to do so is the reduce processing step and increase device integration (Park, [5]).
Re claim 7, Kim modified above teaches the semiconductor memory device of claim 6, further comprising: a filling insulation layer (Park, 256/258, fig16E, [105]) in the peripheral region, the filling insulation layer covering the substrate and the gate line (Park, 240, fig16E, [103]) and including a plurality of contact holes (Park, space holding 290P, fig16E) in communication with the plurality of peripheral bit line recesses, respectively; and a plurality of contact plugs (Park, 290P in 256, fig16E, [137]) respectively filling the plurality of contact holes and electrically connected to the peripheral active region (Park, 116, fig16E), wherein the plurality of contact plugs (Park, 290P in 256, fig16E, [137]) include the same material as the plurality of lower landing pads (Park, 190L, fig23A, [136]; Kim LP1 and LP2 formed as the same material 176=172 and 178=174 [42]).
Re claim 8, Kim modified above teaches the semiconductor memory device of claim 7, wherein the plurality of peripheral bit lines (Park, 290P in 180P/258, fig16E, [137]) pass through the peripheral bit line insulating structure (Park, 180P, fig16E, [122]) and extend inside an upper portion of the filling insulation layer (Park, 258 of 256/258, fig16E, [105]).
Re claim 9, Kim modified above teaches the semiconductor memory device of claim 6, wherein a top surface of each of the plurality of upper landing pads is at the same vertical level as a top surface of the landing pad insulating structure (Park, 180 and 180P in one CMP process, fig14E, [135]), and a top surface of each of the plurality of peripheral bit lines is at the same vertical level as a top surface of the peripheral bit line insulating structure (Park, 290P in 180P CMP, fig16E, [135, 137]).
Re claim 10, Kim modified above teaches the semiconductor memory device of claim 6, wherein a bottom surface of each of the plurality of peripheral bit lines (Park, 290P in 258, fig16E, [137]) is at a lower vertical level than a bottom surface of the peripheral bit line insulating structure (Park, 180P, fig16E).
Re claim 11, Kim teaches a semiconductor memory device (fig2A) comprising:
a substrate (101, fig2A, [20]) including a plurality of active regions (ACT, fig2A, [20]) in a memory cell region (fig2A),
a plurality of bit line structures (BLS, fig 1 and 2A, [20]) extending in parallel with each other in a first horizontal direction (Y, fig1) in the memory cell region;
a plurality of buried contacts (160 and 165, fig2A, [21]) respectively and electrically connected to the plurality of active regions, the plurality of buried contacts (160 and 165, fig2A, [21]) partially filling a space between the plurality of bit line structures (BLS, fig 1 and 2A, [20]);
a plurality of lower landing pads (LP1, fig2A, [21]) in the space between the plurality of bit line structures (BLS, fig 1 and 2A, [20]) and respectively on the plurality of buried contacts (160 and 165, fig2A, [21]);
a landing pad insulating structure (180, fig2A, [20]) in contact with the plurality of bit line structures (BLS, fig 1 and 2A, [20]) and the plurality of lower landing pads (LP1, fig2A, [21]), the landing pad insulating structure (180, fig2A, [20]) including a plurality of landing pad holes (space holding LP2, fig2A, [21]);
a plurality of upper landing pads (LP2, fig2A, [21]) respectively filling the plurality of landing pad holes and respectively connected to the plurality of lower landing pads (LP1, fig2A, [21]);
Kim does not explicitly show a peripheral active region in a peripheral region; a gate line in the peripheral region; a peripheral bit line insulating structure on the gate line, the peripheral bit line insulating structure including a plurality of peripheral bit line recesses; and a plurality of peripheral bit lines respectively filling the plurality of peripheral bit line recesses, wherein a top surface of each of the plurality of upper landing pads, a top surface of the landing pad insulating structure, a top surface of each of the plurality of peripheral bit lines, and a top surface of the peripheral bit line insulating structure are coplanar with one another at the same vertical level.
Park teaches a peripheral active region (116, fig16E) in a peripheral region (fig16E);
a gate line (240, fig16E, [103]) in the peripheral region;
a peripheral bit line insulating structure (180P, fig16E, [122]) on the gate line, the peripheral bit line insulating structure (180P, fig16E, [122]) including a plurality of peripheral bit line recesses (space holding 290P, fig16E, [137]); and
a plurality of peripheral bit lines (290P, fig16E, [137]) respectively filling the plurality of peripheral bit line recesses, wherein a top surface of each of the plurality of upper landing pads, a top surface of the landing pad insulating structure, a top surface of each of the plurality of peripheral bit lines, and a top surface of the peripheral bit line insulating structure are coplanar with one another at the same vertical level (190L, 180, 290P, 180P formed in one CMP process, fig15A-E, [135]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kim and Park to form the Peripheral circuit region together with the core region. The motivation to do so is the reduce processing step and increase device integration (Park, [5]).
Re claim 12, Kim modified above teaches the semiconductor memory device of claim 11, further comprising: a filling insulation layer (Park, 256/258, fig16E, [105]) in the peripheral region, the filling insulation layer covering the substrate and the gate line (Park, 240, fig16E, [103]) and including a plurality of contact holes (Park, space holding 290P, fig16E) in communication with the plurality of peripheral bit line recesses, respectively; and a plurality of contact plugs (Park, 290P in 256, fig16E, [137]) respectively filling the plurality of contact holes and electrically connected to the peripheral active region (Park, 116, fig16E).
Re claim 13, Kim modified above teaches the semiconductor memory device of claim 12, wherein the plurality of peripheral bit lines (Park, 290P in 180P/258, fig16E, [137]) pass through the peripheral bit line insulating structure (Park, 180P, fig16E, [122]) and extend inside an upper portion of the filling insulation layer (Park, 258 of 256/258, fig16E, [105]), and a bottom surface of each of the plurality of peripheral bit lines (Park, 290P in 258, fig16E, [137]) is at a lower vertical level than a bottom surface of the peripheral bit line insulating structure (Park, 180P, fig16E).
Re claim 14, Kim modified above teaches the semiconductor memory device of claim 13, wherein the bottom surface of each of the plurality of peripheral bit lines (Park, 290P in 258, fig16E, [137]) is at the same vertical level as a top surface of each of the plurality of contact plugs (Park, 290P in 256, fig16E, [137]).
Re claim 15, Kim modified above teaches the semiconductor memory device of claim 13, wherein the landing pad insulating structure (Kim, 180, fig2A, [20]) includes a plurality of insulating grooves in a lower portion thereof (Kim, recess part of lower 180, fig2A), the plurality of insulating grooves being respectively filled with the plurality of bit line structures (Kim, BLS, fig 1 and 2A, [20]), and each of the plurality of bit line structures includes a cut part in an upper portion thereof (Kim, top part of BC covered by LP2, fig2A, [39]), the cut part not being covered with the landing pad insulating structure (Kim, 180, fig2A, [20]).
Re claim 16, Kim modified above teaches the semiconductor memory device of claim 12, wherein the landing pad insulating structure includes the same material as the peripheral bit line insulating structure (Park, 180 and 180P in one CMP process, fig14E, [135]), the plurality of upper landing pads (Park, 190L, fig23A, [136]) include the same material as the plurality of peripheral bit lines (Park, 290P, fig16E, [137]), and the plurality of lower landing pads include the same material as the plurality of contact plugs (Kim LP1 and LP2 formed as the same material 176=172 and 178=174 [42]).
Re claim 17, Kim modified above teaches the semiconductor memory device of claim 11, wherein a bottom surface of each of the plurality of upper landing pads (Kim, bottom surface of LP2 at L2, fig6B, [21]) and a top surface of the plurality of lower landing pads (Kim, top surface of LP1 at L2 in contact with LP2, fig6B, [21]) are at a lower vertical level than a topmost surface of each of the plurality of bit line structures (Kim, BLS above L1, fig 1 and 6B, [20]), and the top surface of each of the plurality of upper landing pads (Kim, top surface of LP2, fig6B, [21]) is at a higher vertical level than the topmost surface of each of the plurality of bit line structures (Kim, BLS, fig 1 and 6B, [20]).
Re claim 18, Kim teaches a semiconductor memory device (fig2A) comprising:
a substrate (101, fig2A, [20]) including a plurality of active regions (ACT, fig2A, [20]) in a memory cell region (fig2A);
a plurality of word lines (WLS, fig1 and 2A, [20]) respectively in a plurality of word line trenches in the substrate (fig1 and 2A), the plurality of word line trenches extending in parallel with each other in a first horizontal direction (X, fig1) in the memory cell region;
a plurality of bit line structures (BLS, fig 1 and 2A, [20]) extending on the plurality of word lines in parallel with each other in a second horizontal direction (Y, fig1) that is perpendicular to the first horizontal direction,
wherein each of the plurality of bit line structures (BLS, fig 1 and 2A, [20]) includes a bit line (141 of BL, fig2A, [54]), an insulating capping line (BC, fig2A, [56]) covering the bit line, and a pair of insulating spacer structures (SS, fig2A, [58]) respectively covering opposite side walls of each of the bit line and the insulating capping line;
a plurality of buried contacts (160 and 165, fig2A, [21]) respectively and electrically connected to the plurality of active regions, the plurality of buried contacts (160 and 165, fig2A, [21]) partially filling a space between the plurality of bit line structures (BLS, fig 1 and 2A, [20]);
a plurality of lower landing pads (LP1, fig2A, [21]) in the space between the plurality of bit line structures and respectively on the plurality of buried contacts;
a landing pad insulating structure (180, fig2A, [20]) in contact with the plurality of bit line structures (BLS, fig 1 and 2A, [20]) and the plurality of lower landing pads (LP1, fig2A, [21]), the landing pad insulating structure including a plurality of landing pad holes (space holding LP2, fig2A, [21]);
a plurality of upper landing pads (LP2, fig2A, [21]) respectively filling the plurality of landing pad holes and respectively connected to the plurality of lower landing pads;
a plurality of capacitor structures (CAP, fig2A, [20]) including a plurality of lower electrodes (192, fig2A, [62]) respectively and electrically connected to the plurality of upper landing pads (LP2, fig2A, [21]), an upper electrode (196, fig2A, [62]), and a capacitor dielectric layer (194, fig2A, [62]) between the plurality of lower electrodes and the upper electrode;
wherein the landing pad insulating structure (180, fig2A, [20]) includes a plurality of insulating grooves (recess part of lower 180, fig2A) in a lower portion thereof, the plurality of insulating grooves being respectively filled with the plurality of bit line structures (BLS, fig 1 and 2A, [20]).
Kim does not explicitly show a peripheral active region in a peripheral region; a gate line in the peripheral region; a filling insulation layer in the peripheral region, the filling insulation layer covering the substrate and the gate line and including a plurality of contact holes; a plurality of contact plugs respectively filling the plurality of contact holes and electrically connected to the peripheral active region; a peripheral bit line insulating structure on the gate line, the peripheral bit line insulating structure including a plurality of peripheral bit line recesses in communication with the plurality of contact holes, respectively; and a plurality of peripheral bit lines respectively filling the plurality of peripheral bit line recesses and electrically connected to the plurality of contact plugs, wherein the landing pad insulating structure includes a plurality of insulating grooves in a lower portion thereof, the plurality of insulating grooves being respectively filled with the plurality of bit line structures, and the plurality of peripheral bit lines pass through the peripheral bit line insulating structure and extend inside an upper portion of the filling insulation layer.
Park teaches a peripheral active region (116, fig16E) in a peripheral region (fig16E);
a gate line (240, fig16E, [103]) in the peripheral region;
a filling insulation layer (256/258, fig16E, [105]) in the peripheral region, the filling insulation layer (256/258, fig16E, [105]) covering the substrate and the gate line (240, fig16E, [103]) and including a plurality of contact holes (space holding 290P, fig16E);
a plurality of contact plugs (290P in 256, fig16E, [137]) respectively filling the plurality of contact holes and electrically connected to the peripheral active region;
a peripheral bit line insulating structure (180P, fig16E, [122]) on the gate line, the peripheral bit line insulating structure including a plurality of peripheral bit line recesses (space holding 290P, fig16E, [137]) in communication with the plurality of contact holes, respectively; and
a plurality of peripheral bit lines (290P in 180P/258, fig16E, [137]) respectively filling the plurality of peripheral bit line recesses and electrically connected to the plurality of contact plugs (290P in 256, fig16E, [137]), and
the plurality of peripheral bit lines (290P in 180P/258, fig16E, [137]) pass through the peripheral bit line insulating structure (180P, fig16E, [122]) and extend inside an upper portion of the filling insulation layer (258 of 256/258, fig16E, [105]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Kim and Park to form the Peripheral circuit region together with the core region. The motivation to do so is the reduce processing step and increase device integration (Park, [5]).
Re claim 19, Kim modified above teaches the semiconductor memory device of claim 18, wherein a top surface of each of the plurality of upper landing pads (Kim, top surface of LP2, fig6B, [21]), a top surface of the landing pad insulating structure (Kim, top surface of 180, fig6B, [20]), a top surface of each of the plurality of peripheral bit lines (Park, top surface of 290P, fig16E), and a top surface of the peripheral bit line insulating structure (Park, top surface of 180P, fig16E) are coplanar with one another at the same vertical level (Park, 180 and 180P in one CMP process, fig14E, [135]), a bottom surface of each of the plurality of upper landing pads (Kim, bottom surface of LP2 at L2, fig6B, [21]) and a top surface of the plurality of lower landing pads (Kim, top surface of LP1 at L2 in contact with LP2, fig6B, [21]) are at a lower vertical level than a topmost surface of each of the plurality of bit line structures (Kim, BLS above L1, fig 1 and 6B, [20]), and a bottom surface of the plurality of lower landing pads (Kim, bottom surface of LP1, fig6B, [21]) is at a higher vertical level than a top surface of the bit line (Kim, 141 of BL, fig6A, [54]) of each of the plurality of bit line structures (Kim, BLS above L1, fig 1 and 6A, [20]).
Re claim 20, Kim modified above teaches the semiconductor memory device of claim 18, wherein the landing pad insulating structure (Kim, 180, fig2A, [20]; Park, 180 as SiN, fig14E, [124, 135]) and the peripheral bit line insulating structure include silicon nitride (Park, 180P as SiN, fig14E, [124, 135]), and the plurality of upper landing pads and the plurality of peripheral bit lines include tungsten (Kim, Lp1 and LP2 as W, fig6A, claim 6).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIAOMING LIU/Examiner, Art Unit 2812
Prosecution Insights