DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I, Figs 1-7 in the reply filed on 06/24/2026 is acknowledged. The traversal is on the ground(s) that the claims identify chips in order of introduction in the claims, and the claimed embodiments of claims 1 and 9 are the same. This is not found persuasive because a second crack detection line of claim 9 contacts a surface of the first semiconductor chip opposite to the interface. In claim 1, a second crack detection line contacting a surface of the second semiconductor chip opposite to the interface. Meanwhile, a crack detector did not move as the chips were allegedly renamed, “a crack detector in the second semiconductor chip” is a limitation of both claim 1 and claim 9. If claim 9 merely renamed the chips in the order of introduction in the claims (p.2, first paragraph of arguments), that would place a crack detector in the first semiconductor chip rather than the second semiconductor chip.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a type" in lines 3 and 4. The antecedent basis for this limitation in the claim is unclear. The Examiner suggests using a second type in line 3 and a first type in line 4.
Claims 2-8 are rejected as claims dependent on claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et. al., U.S. Pat. Pub. 2021/0074596, hereafter Kim, in view of Giacomini et. al., U.S. Pat. Pub. 2023/0168300, hereafter Giacomini.
Regarding claim 1, Kim discloses (Figs 16, 18, 26, see Fig. 26) a semiconductor device comprising: a first semiconductor chip [SD1];
a second semiconductor chip [SD2] stacked on the first semiconductor chip [SD1], wherein a second type of the second semiconductor chip is different (par. [0094], Fig. 18, one is memory cell region, the other peripherals circuit region) from a first type of the first semiconductor chip [SD2]; and
a crack detection circuit [OCDSd] comprising:
a first crack detection line (the entire zigzag line in Fig. 26, see also OCDS in Fig. 7) repeatedly passing through an interface between the first semiconductor chip [SD1] and the second semiconductor chip [SD2];
a second crack detection line (the same line shown in Fig. 26) comprising a bonding pad [MPB] or a through-via structure [TSV2] contacting a surface (bottom surface) of the second semiconductor chip [SD2] opposite to the interface (tope surface of [SD2]) ; and
a crack detector CDET [520] (Fig. 16), the crack detector being configured to:
output a first test signal [TSI1] to the first crack detection line [ENI1], receive a first reception signal [TSO2] from the first crack detection line [ENO1], output a second test signal [TSI2] to the second crack detection line [ENI2], and receive a second reception signal [TSO2] from the second crack detection line [ENO2].
Kim fails to explicitly disclose the crack detector in the second semiconductor chip.
However, Giacomini discloses (Fig. 1) the crack detector [8],[9] in the second semiconductor chip [10] (par. [0003].
It would have been obvious to one of ordinary skill in the art prior to effective date of the instant application to place crack detector on in the second semiconductor chip, as taught by Giacomini, because Giacomini teaches (par. [0008]) measuring the electrical continuity of the sensor 1 during EWS (Electrical Wafer Sorting”) and FT (“Final Test”) through the detector cell 8 allows to detect, and screen out, portions of the seal ring having cracks. Affecting a specific bin and SBL to this test will allow a correct monitoring of the defect rate and to take adequate actions in case of need.
Regarding claim 5, Kim in view of Giacomini discloses everything as applied above. Kim in view of Giacomini fails to explicitly disclose wherein an area of the first semiconductor chip in a horizontal direction is less than an area of the second semiconductor chip in the horizontal direction.
However, it would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify areas of the first and second semiconductor chips in the horizontal direction to meet the claim because a change in relative size is normally considered within the ability of one of ordinary skill in the art. In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984) (MPEP, Latest Edition, 2144.04.IV.B)
Regarding claim 6, Kim in view of Giacomini discloses everything as applied above. Kim further discloses (Fig. 7, 27A)
wherein the first semiconductor chip comprises a central area [CREG] in which semiconductor elements [MC] (memory cells) are formed and a boundary area [EREG] around the central area [CREG], and
wherein the first crack detection line [OCDSu] is provided in the boundary area [EREG].
Regarding claim 7, Kim in view of Giacomini discloses everything as applied above. Giacomini further discloses (Fig. 5, par. [0051]-[0055]) wherein the crack detector comprises: a plurality of first inverter circuits configured to transmit the first test signal to the first crack detection line in response to a first enable signal; and
a plurality of second inverter circuits configured to transmit the second test signal to the second crack detection line in response to a second enable signal ( First and second circuits can be the same).
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to use inverter circuits of Giacomini to transmit test signals of Kim, because this allows for the test circuit to be turned off when the test is not performed.
Regarding claim 8, Kim in view of Giacomini discloses everything as applied above. Kim further discloses (Fig. 26)
wherein the first crack detection line comprises a first wiring pattern [HLT], a first bonding pad [MP2] on the first semiconductor chip [SD1], a second wiring pattern [HLB], and a second bonding pad [MPP2] on the second semiconductor chip [SD2],
wherein the first wiring pattern comprises a horizontal pattern [HLT] on a metal layer [ML1] of the first semiconductor chip[SD1] and a vertical pattern [TSV1] connecting the horizontal pattern to the first bonding pad [MP2], and
wherein the second wiring pattern comprises a horizontal pattern [HLB] on a metal layer of the second semiconductor chip [SD2] and a vertical pattern [TSV2] connecting the horizontal pattern [HLB] to the second bonding pad [PP2].
Allowable Subject Matter
Claims 2-4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 2, Kim in view of Giacomini discloses everything as applied above. Kim in view of Giacomini and other references of record fails to explicitly disclose wherein the first crack detection line and the second crack detection line are physically separated from each other, and
wherein each of first crack detection line and the second crack detection line have a zigzag pattern (The first and second crack detection lines of Kim in view of Giacomini are not physically separated from each other).
Regarding claim 3, Kim in view of Giacomini discloses everything as applied above. Kim further discloses (Figs 16, 18, 26, see Fig. 26) wherein the second semiconductor chip [SD2] is provided under the first semiconductor chip [SD1],
Kim in view of Giacomini fails to explicitly disclose or make obvious:
wherein the semiconductor device further comprises a third semiconductor chip provided under the second semiconductor chip,
wherein the second crack detection line further comprises a wiring pattern in the second semiconductor chip, and a wiring pattern in the third semiconductor chip, and
wherein the second crack detection line repeatedly passes through an interface between the second semiconductor chip and the third semiconductor chip.
Regarding claim 4, Kim in view of Giacomini discloses everything as applied above. Kim in view of Giacomini fails to explicitly disclose or make obvious
wherein the second semiconductor chip is provided on top of the first semiconductor chip,
wherein the semiconductor device further comprises a third semiconductor chip provided on top of the second semiconductor chip,
wherein the second crack detection line comprises the through-via structure, a wiring pattern in the second semiconductor chip, and a wiring pattern in the third semiconductor chip, and
wherein the second crack detection line repeatedly passes through an interface between the second semiconductor chip and the third semiconductor chip.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VICTOR V BARZYKIN/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights