Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1 -4 , 9 , 16-14 and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Li et al. ( US 2015 / 0279431 A1 ). Regarding independent claim 1 : Li teaches (e.g., Fig. 1) a n integrated circuit device comprising: a substrate ([0015]: 120) ; one or more memory chips ([0015]: 105) stacked on top of said substrate; and a logic chip ([0015]: 102b) stacked on top of said one or more memory chips; wherein said logic chip communicates with said substrate via through-silicon vias ([0016]: 130) located in said one or more memory chips. Regarding claim 2 : Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends, wherein said through-silicon vias are utilized for power connections ([0031]; the through-silicon vias are capable of being used for power connections during operation) . Applicant is reminded that when the structure recited in the reference is substantially identical to that of the claims, the claimed properties or functions are presumed inherent. MPEP 2112.01 (I). Regarding claim 3 : Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends, wherein said through-silicon vias are utilized for signaling connections ([0032]: the through-silicon vias are capable of being used for signal ing connections during operation) . Applicant is reminded that when the structure recited in the reference is substantially identical to that of the claims, the claimed properties or functions are presumed inherent. MPEP 2112.01 (I). Regarding claim 4 : Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends, wherein said one or more memory chips correspond to high bandwidth memory chips ([0020]: one or more memory chips correspond to high bandwidth memory chips; since the structure is taught the functions are deemed inherent; MPEP 2112.01 (i) ) . Regarding claim 9: Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends. wherein said logic chip comprises a processor (Li: [0020]). Regarding claim 13: Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends. wherein said one or more memory chips ([0020]; 103) are stacked on top of said substrate via a silicon spreader ([0015] and [0020]: 105). Regarding claim 14: Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends. wherein a first portion of said through-silicon vias ([0016]: 130) are connected to a first core logic domain within said one or more memory chips ([0015] and [0020]: 103) at a first voltage level, wherein a second portion of said through-silicon vias ([0016]: 130) are connected to a second core logic domain within said one or more memory chips ([0015] and [0020]: 103) at a second voltage level, wherein said second voltage level is higher than said first voltage level. Applicant is reminded that when the structure recited in the reference is substantially identical to that of the claims, the claimed properties or functions are presumed inherent. MPEP 2112.01 (I). Regarding claim 20: Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends. wherein one of said one or more memory chips is used as a quad-level cell flash memory ([0020]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 5- 8 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. ( US 2015 / 0279431 A1 ) in view of Saen et al. ( US 2010 / 0008058 A1 ). Regarding claim 5 : Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends. Li does not expressly teach a first portion of said through-silicon vias terminate on one of said one or more memory chips. Saen teaches (e.g., Fig. 1) an integrated circuit device comprising through-silicon vias ([0027]: TVSIG1 and TVSIG2) and memory chips ([0027]: MEMLSI); Saen further teaches that a first portion of said through-silicon vias ([0027]: TVSIG2) terminate on one of said one or more memory chips ([0027]: MEMLSI). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention , to include in the device of Li, the first portion of said through-silicon vias terminat ing on one of said one or more memory chips, as taught by Saen, for the benefits of selectively controlling the integrated circuit and reducing interconnect density leading to a reduced signal interference. Regarding claim 6 : Li and Saen teach the claim limitation of the claim limitation of the integrated circuit device as recited in claim 5, on which this claim depends. wherein said first portion of said through-silicon vias (Saen: TVSIG2) are used to communicate with said one of said one or more memory chips (Saen: [0027]: MEMLSI) . Regarding claim 7 : Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends. Li does not expressly teach that a second portion of said through-silicon vias are electronically disconnected from a specific memory chip of said one or more memory chips. Saen teaches (e.g., Fig. 1) an integrated circuit device comprising through-silicon vias ([0027]: TVSIG1 and TVSIG2) and memory chips ([0027]: MEMLSI); Saen further teaches that a second portion of said through-silicon vias ([0027]: TVSIG2) are electronically disconnected from a specific memory chip of said one or more memory chips ([0027]: MEMLSI). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention , to include in the device of Li, the second portion of said through-silicon vias being electronically disconnected from a specific memory chip of said one or more memory chips, as taught by Saen, for the benefits of selectively controlling the integrated circuit and reducing interconnect density leading to a reduced signal interference. Regarding claim 8 : Li and Saen teach the claim limitation of the claim limitation of the integrated circuit device as recited in claim 7, on which this claim depends. Li as modified by Saen teaches that said second portion of said through-silicon vias ([0027]: TVSIG2) are used for enabling said logic chip to communicate with said substrate (Saen: [0039]) . Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. ( US 2015 / 0279431 A1 ) in view of Kawasaki et al. ( US 2019 / 0088625 A1 ). Regarding claim 10 : Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends. Lee does not expressly teach that said logic chip comprises a buffer. Kawasaki teaches an integrated circuit device comprising a logic chip ([0043] and [0058]: 30) comprising a buffer ([0043] and [0058]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention , to include in the integrated circuit device of Li, the logic chip comprising a buffer, as taught by Kawasaki. For the benefits, of insulating the device from disturbance during operation. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. ( US 2015 / 0279431 A1 ) in view of Jang et al. ( US 2021 / 0327812 A1 ). Regarding claim 11 : Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends. Li does not expressly teach that said logic chip is stacked on top of said one or more memory chips via decoupling capacitors. Jang teaches (Fig. 15C) an integrated circuit device comprising a logic chip (P ; see [0054], claim 15 ) stacked on top of one or more memory chips (C see [0054]; claim 15 ) via decoupling capacitors ( claim 15 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention , to include in the device of Li, the logic chip being stacked on top of said one or more memory chips via decoupling capacitors, as taught by Jang, for the benefits of stabilizing the power supply and reducing noise. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. ( US 2015 / 0279431 A1 ) in view of Yu et al. ( US 2022 / 0262783 A1 ). Regarding claim 12 : Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends. Li does not expressly teach that said logic chip is stacked on top of said one or more memory chips via a voltage regulator. Yu teaches (e.g., Figs. 5A-5C and Fig. 10B) an integrated circuit device comprising a logic chip ([0073]: 10L) being stacked on top of one or more memory chips ([0073]: 50) via a voltage regulator ([0019] and [0102]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention , to include in the device of Li, the logic chip being stacked on top of said one or more memory chips via a voltage regulator, as taught by Yu, for the benefits of stabilizing the power supply and reducing noise Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. ( US 2015 / 0279431 A1 ) in view of Wang et al. ( US 2024 / 0321759 A1 ). Regarding claim 15 : Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 14, on which this claim depends. Li does not expressly teach that said logic chip comprises a step-down switched capacitor power converter circuit. Wang teaches an integrated circuit comprising a logic chip comprises a step-down switched capacitor power converter circuit ([0084]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention , to include in the device of Li, the logic chip comprising a step-down switched capacitor power converter circuit, as taught by Li, for the benefits of protecting devices from over-voltage breakdown. Regarding claim 17: Li and Wang teach the claim limitation of the claim limitation of the integrated circuit device as recited in claim 15, on which this claim depends. wherein said step-down switched capacitor power converter circuit produces a regulated voltage that is at a lower voltage level than a voltage level of said one or more memory chips (Wang: [0084]: inherent for a step-down converter). Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. ( US 2015 / 0279431 A1 ) in view of Wang et al. ( US 2024 / 0321759 A1 ) as applied above and further in view of Giuliano ( US 2017 / 0244318 A1 ). Regarding claim 16 : Li and Wang teach the claim limitation of the claim limitation of the integrated circuit device as recited in claim 15, on which this claim depends. Although, Li as modified by Wang does not expressly teach that said step-down switched capacitor power converter circuit corresponds to a 2:1 step-down converter ; Giuliano teaches a device comprising a step-down switched capacitor power converter circuit correspond ing to a 2:1 step-down converter ([0301]) Therefore, i t would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include in the integrated circuit device of Li a s modified by Wan g, the step-down switched capacitor power converter circuit correspond ing to a 2:1 step-down converter , as taught by Giuliano, for the benefits of protecting the load device from over-voltage damage. Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. ( US 2015 / 0279431 A1 ) in view of Parekh et al. ( US 2023 / 0049683 A1 ). Regarding claim 18 : Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1, on which this claim depends. Li does not expressly teach that a portion of contacts of said through-silicon vias in said one or more memory chips are connected to said substrate using a redistribution layer process. Parekh teaches (e.g., Figs. 1 and 2C) an integrated circuit comprising a portion of contacts of through-silicon vias ([0032], [0049] and [0056]: TSV) in one or more memory chips ([0032] and [0046]: 202) are connected to a substrate ([0054]: 218) using a redistribution layer process ([0053]). Therefore, i t would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include in the device of Li, the portion of contacts of said through-silicon vias in said one or more memory chips being connected to said substrate using a redistribution layer process, as taught by Parekh, for the benefits of increasing the contact region and thus ensures good electrical communication for signal processing. Regarding claim 19 : Li teaches the claim limitation of the claim limitation of the integrated circuit device as recited in claim 1 8 , on which this claim depends , wherein said redistribution layer process is used to expand a contact pitch (Parekh: [0053]: inherent function of a redistribution layer) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT HERVE-LOUIS Y ASSOUMAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-2606 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F: 08:30 AM-5:30 PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT DAVIENNE MONBLEAU can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-1945 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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